Semiconductor memory device

Abstract

A p layer extends parallel to the substrate, part of the p layer is coated with a first gate insulating layer, a first gate conductor layer covers part of the first gate insulating layer, a second gate insulating layer covers part of the p layer, a second gate conductor layer covers part of the second gate insulating layer, and an n+ layer and another n+ layer are provided in part of the p layer interposed between the first and second gate conductor layers. The first gate conductor layer functions as a gate, one of the n+ layers functions as a source, and the other n+ layer functions as a drain to perform a MOSFET operation. Respective voltages of a bit line, a source line, a word line, a plate line are operated so as to perform a memory operation of an FX-RAM.

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