Nanostructure field-effect transistor devices and methods of forming

TW202630756APending Publication Date: 2026-07-16TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
TW114124018
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-05-01
Filing Date
2025-06-25
Publication Date
2026-07-16
Patent Text Reader

Abstract

A dielectric layer is formed at a bottom of a source / drain opening for a p-type source / drain region of a nanostructure field-effect transistor (NSFET) device. Next, a source / drain region with a multi-layered structure is formed in the source / drain opening over the dielectric layer. Forming the source / drain region includes forming a first epitaxial material in the source / drain opening, the first epitaxial material including discrete portions disposed along sidewalls of a channel material of the NSFET device exposed to the source / drain opening. A second epitaxial material is then formed on the first epitaxial material and partially fills the source / drain opening. The second epitaxial material may extend continuously from a first discrete portion of the first epitaxial material to a second discrete portion of the first epitaxial material.
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