A monolithically integrated GAN cascode

Abstract

A monolithically integrated GaN cascode includes a substrate, a buffer layer, a GaN channel layer, an AlGaN layer, a source, a drain, an E-gate, a D-gate, and a node electrode. The E-gate disposed on the aluminum gallium nitride layer and includes a P-type doped gallium nitride layer, and an E-gate conductive layer disposed on the P-type doped gallium nitride layer. The D-type gate electrically connects to the source and includes a dielectric layer and a D-type gate conductive layer. The node electrode is electrically connected to the D-type gate. A junction band characteristic of the aluminum gallium nitride layer and the gallium nitride channel layer is indirectly changed by disposing the P-type doped gallium nitride layer, so that the transistor has a normally off property. Since the transistor does not have a fluoride ion implantation region, the transistor has better electrical properties in comparison with the prior art.

Description

[Technical Field]

[0001] This invention relates to a stacked transistor, and more particularly to a gallium nitride stacked transistor. [Previous Technology]

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are widely used in integrated circuits. Because the two-dimensional electron gas (2DEG) in GaN naturally forms conductive channels, it can function as a normally-on transistor and possesses high electron mobility. However, compared to normally-on transistors, normally-off transistors offer higher safety operating conditions and greater convenience in gate drive circuitry, thus having a wider range of applications.

[0003] A common technique for implementing normally-off GaN transistors is cascaded transistors. It is fabricated by connecting a normally-on (depletion mode, D mode) GaN HEMT in series with a normally-off (enhancement mode, E mode) Silicon Metal Oxide Semiconductor Field Effect Transistor (Si MOSFET). The Si MOSFET acts as the driving element, and the GaN HEMT acts as the load, thus achieving characteristics equivalent to a normally-off GaN transistor. However, the above structure of a D-mode GaN HEMT connected in series with an E-mode Si MOSFET has many drawbacks, such as Si MOSFET limiting high-temperature operation, increasing packaging complexity, increasing the overall structural size, and introducing parasitic inductance. This parasitic inductance can also negatively affect the switching characteristics of the transistor.

[0004] Another technology for realizing normally-off GaN transistors is integrated gallium nitride stacked transistors. Referring to Figure 1, the integrated gallium nitride stacked transistor includes a silicon substrate P1, a buffer layer P2, a gallium nitride channel layer P3, an aluminum gallium nitride barrier layer P4, a gallium nitride capping layer P5, a dielectric layer P6, a source P7, a drain P8, an enhancement-mode gate P9, a depletion-mode gate P10, a passivation layer P11, and a source field plate P12. Among them, the area of ​​the gallium nitride capping layer P5 and the aluminum gallium nitride barrier layer P4 located below the enhancement-mode gate P8 forms a fluorine ion implantation region F due to fluorine ion implantation. Because the fluorine ion implantation region F alters the interface characteristics between the aluminum gallium nitride barrier layer P4 and the gallium nitride channel layer P3, it blocks the formation of the two-dimensional electron gas 2DEG, giving the enhancement-mode gate P9 the characteristics of a normally-off gate. Furthermore, the region below the depletion-mode gate P10 retains the characteristics of a normally-on gate because it has not undergone fluorine ion implantation. Therefore, the series connection of these two components constitutes a modular gallium nitride stacked transistor with normally-off characteristics. However, since the aforementioned modular gallium nitride stacked transistor undergoes an ion implantation process, the bombardment of high-energy ions during the process can damage the crystal structure, thereby degrading the transistor's electrical properties. [Summary of the Invention]

[0005] Therefore, the object of the present invention is to provide a monolithic gallium nitride stacked transistor that can at least overcome the disadvantages of the prior art.

[0006] Thus, the monolithic gallium nitride stacked transistor of the present invention comprises a substrate, a buffer layer, a gallium nitride channel layer, an aluminum gallium nitride layer, a source, a drain, an enhancement-mode gate, a depletion-mode gate, and a node electrode.

[0007] The buffer layer is disposed on the substrate. The gallium nitride channel layer is disposed on the buffer layer. The aluminum gallium nitride layer is disposed on the gallium nitride channel layer. The source is disposed on the aluminum gallium nitride layer. The drain is disposed on the aluminum gallium nitride layer. The enhancement-mode gate is located between the source and the drain, and is disposed on the aluminum gallium nitride layer, and includes a p-type doped gallium nitride layer and an enhancement-mode gate conductive layer disposed on the p-type doped gallium nitride layer. The depletion-mode gate is located between the source and the drain, and is electrically connected to the source, and is disposed on the aluminum gallium nitride layer, and includes a depletion-mode gate conductive layer. The node electrode is disposed on the gallium nitride channel layer, and is located between the enhancement-mode gate and the depletion-mode gate, and is electrically connected to the depletion-mode gate.

[0008] The advantages of this invention are as follows: Since the enhancement-mode gate of this invention includes a P-type doped gallium nitride layer disposed on the aluminum gallium nitride layer, it indirectly alters the bandgap characteristics at the interface between the aluminum gallium nitride layer and the gallium nitride channel layer, thereby blocking the formation of a two-dimensional electron gas and giving the enhancement-mode gate the characteristics of a normally-off gate. Therefore, the series connection of the normally-on GaN HEMT and the normally-off GaN HEMT constitutes a gallium nitride stacked transistor with normally-off characteristics. Since this transistor does not have a fluorine ion implantation region, its crystal structure will not be destroyed by high-energy ions. Compared to conventional integrated gallium nitride stacked transistors that form enhancement-mode gates with fluorine ion implantation regions, it possesses superior electrical characteristics. Furthermore, this transistor is composed of a normally-on GaN HEMT and a normally-off GaN HEMT. Compared with conventional stacked transistors composed of GaN HEMT and Si MOSFET, it has advantages such as high temperature resistance, reduced packaging complexity, and reduced parasitic inductance.

Implementation Method

[0009] Before the present invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.

[0010] Referring to Figure 2, the first embodiment of the monolithic gallium nitride stacked transistor of the present invention is formed by connecting a normally on GaN HEMT and a normally off GaN HEMT in series. Referring to Figure 3, the first embodiment includes a substrate 1, a buffer layer 2, a gallium nitride channel layer 3, an aluminum gallium nitride layer 4, a source 5, a drain 6, an enhancement-mode gate 7, a depletion-mode gate 8, a node electrode 9, an insulating layer 10, a protective layer 11, a source field plate 12, and a dielectric layer 13.

[0011] The substrate 1 is, for example, but not limited to, a silicon substrate, a silicon carbide substrate, a sapphire substrate, or an insulating silicon substrate. The buffer layer 2 is disposed on the substrate 1. The gallium nitride channel layer 3 is disposed on the buffer layer 2. The aluminum gallium nitride layer 4 is disposed on the gallium nitride channel layer 3.

[0012] The source electrode 5 is disposed on the upper side of the aluminum gallium nitride layer 4 and includes a source layer 51, a source conductive pillar 52, and a source pad 53 arranged sequentially from bottom to top. The drain electrode 6 is disposed on the upper side of the aluminum gallium nitride layer 4 and includes a drain layer 61, a drain conductive pillar 62, and a drain pad 63 arranged sequentially from bottom to top on the aluminum gallium nitride layer 4. The source layer 51 and the drain layer 61 are, for example, but not limited to, Ti / Al / Ti / Au metal layers. The source conductive pillar 52, the drain conductive pillar 62, the source pad 53, and the drain pad 63 are, for example, but not limited to, Ni / Au metal layers.

[0013] The enhancement-mode gate 7 is located between the source 5 and the drain 6, and is disposed on the aluminum gallium nitride layer 4. It includes, from bottom to top, a P-type doped gallium nitride layer 71, an enhancement-mode gate conductive layer 72, and an enhancement-mode gate pad 73. The depletion-mode gate 8 is located between the source 5 and the drain 6, and is disposed on the aluminum gallium nitride layer 4. It includes, from bottom to top, a depletion-mode gate conductive layer 81 and a depletion-mode gate pad 82. The depletion-mode gate pad 82 is electrically connected to the source pad 53 (not shown). The enhancement-mode gate conductive layer 72, the depletion-mode gate conductive layer 81, the enhancement-mode gate pad 73, and the depletion-mode gate pad 82 are, for example, but not limited to, Ni / Au metal layers.

[0014] The node electrode 9 is disposed on the upper side of the aluminum gallium nitride layer 4 and located between the enhancement-mode gate 7 and the depletion-mode gate 8. It includes, from bottom to top, a node electrode layer 91, a node electrode conductive pillar 92, and a node electrode pad 93. The node electrode pad 93 is electrically connected to the depletion-mode gate pad 82. The node electrode 9 serves as a common electrode for both normally-on and normally-off GaN HEMTs and as a node connecting the two in series.

[0015] The insulating layer 10 fills the space between the source electrode 5, the enhancement gate 7, the node electrode 9, the depletion gate 8, and the drain electrode 6, thereby providing insulation. The protective layer 11 covers the source electrode 5, the drain electrode 6, the enhancement gate 7, the depletion gate 8, and the node electrode 9, and is located above the insulating layer 10, thereby providing insulation against external moisture. The materials of the insulating layer 10 and the protective layer 11 are, for example, but not limited to, silicon nitride (SiNx).

[0016] The source field plate 12 is located at intervals on the side of the depletion gate conductive layer 81 away from the substrate 1, and is electrically connected to the source 5. The arrangement of the source field plate 12 enables the bias voltage applied to the depletion gate 8 to more effectively dissipate the hot electrons in the aluminum gallium nitride layer 4, so as to avoid the hot electrons repelling the electrons in the gallium nitride channel layer 3.

[0017] The dielectric layer 13 is located between the aluminum gallium nitride layer 4 and the depletion gate layer 81. Furthermore, the dielectric layer 13 extends to cover the outside of the depletion gate conductive layer 81, and extends to the outside of the drain layer 61 of the drain 6, the outside of the node electrode 9, the outside of the E-type gate conductive layer 72 of the enhancement gate 7, and the outside of the source layer 51 of the source 5.

[0018] In this first embodiment, since the dielectric layer 13 is not provided between the enhanced gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the enhanced gate 7, the enhanced gate conductive layer 72 directly contacts the P-type doped gallium nitride layer, thus forming a metal-semiconductor (MS) structure. The dielectric layer 13 is provided between the depletion gate conductive layer 81 and the aluminum gallium nitride layer 4 of the depletion gate 8, thus forming a metal-insulator-semiconductor (MIS) structure.

[0019] In a variation of the first embodiment, the dielectric layer 13 is located between the enhancement gate conductive layer 72 and the p-type doped gallium nitride layer 71 of the enhancement gate 7, thereby forming a MIS structure on the enhancement gate 7. However, the dielectric layer 13 is not provided between the depletion gate conductive layer 81 and the aluminum gallium nitride layer 4 of the depletion gate 8, and the depletion gate conductive layer 81 of the depletion gate 8 directly contacts the aluminum gallium nitride layer 4 to form an MS structure.

[0020] In another variation of the first embodiment, the dielectric layer 13 is not provided between the enhanced gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the enhanced gate 7, nor between the depletion gate conductive layer 81 and the aluminum gallium nitride layer 4 of the depletion gate 8. Therefore, the enhanced gate 7 and the depletion gate 8 are both MS structures.

[0021] In another variation of the first embodiment, the dielectric layer 13 may be located simultaneously between the enhanced gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the enhanced gate 7, and between the depletion gate conductive layer 81 and the aluminum gallium nitride layer 4 of the depletion gate 8. Therefore, the enhanced gate 7 and the depletion gate 8 are both MIS structures.

[0022] Figure 4 is a schematic diagram of the energy band structure of the depletion gate 8, omitting the dielectric layer 13. As a normally open gate, the depletion gate 8 naturally forms a two-dimensional electron gas (2DEG) in the gallium nitride channel layer 3 due to the energy band characteristics at the interface between the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3, thus exhibiting a negative threshold voltage. Referring to Figure 5, the enhancement gate 7, as a normally closed gate, indirectly alters the energy band characteristics at the interface between the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3 by providing a P-type doped gallium nitride layer 71 between the aluminum gallium nitride layer 4 and the enhancement gate conductive layer 72, thereby blocking the formation of the two-dimensional electron gas 2DEG and exhibiting a positive threshold voltage.

[0023] Therefore, the series connection of the normally-on GaN HEMT and the normally-off GaN HEMT constitutes a single-piece gallium nitride stacked transistor with normally-off characteristics. Furthermore, since the first embodiment does not have a fluorine ion implantation region, the crystal structure of the transistor will not be destroyed by high-energy ions, and it has better electrical characteristics than the prior art.

[0024] Referring to Figure 6, the second embodiment of the monolithic gallium nitride stacked transistor of the present invention differs from the first embodiment in that the source layer 51 of the source 5 and the drain layer 61 of the drain 6 are embedded in the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3. Since the structure of the second embodiment is largely the same as that of the first embodiment, only the differences will be described below, and the similarities will not be repeated.

[0025] In this second embodiment, since the source layer 51 and the drain layer 61 are embedded in the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3, and the source layer 51 and the drain layer 61 are in direct contact with the gallium nitride channel layer 3, the series resistance of the source 5 and the drain 6 can be reduced.

[0026] As mentioned above, the substrate 1 of the monolithic gallium nitride stacked transistor of the present invention can be selected from silicon substrate, silicon carbide substrate, sapphire substrate, or insulator silicon substrate. Among them, the silicon carbide substrate has higher hardness and excellent thermal conductivity and high voltage resistance compared with other substrates, and can enable the transistor to have better switching characteristics.

[0027] Figure 7 is a comparison of the transistor characteristic curves and external transconductance of the silicon carbide substrate and the silicon substrate used in the second embodiment. In the second embodiment, the threshold voltage of the silicon carbide substrate is 0.7V, the drain current is 15.2A, the maximum external transconductance is 15.5 mS / mm, and the Ion / Ioff ratio is 5.4 × 10⁶. In contrast, the threshold voltage of the silicon substrate used in the second embodiment is 0.5V, the drain current is 10.6A, the maximum external transconductance is 15.3 mS / mm, and the Ion / Ioff ratio is 2.7 × 10⁵.

[0028] Figure 8 is a comparison diagram of the output characteristics of the silicon carbide substrate and the silicon substrate used in the second embodiment. The on-resistance of the silicon carbide substrate used in the second embodiment is 52 Ω-mm, while the on-resistance of the silicon substrate used in the second embodiment is 65 Ω-mm.

[0029] Figure 9 is a comparison diagram of the breakdown voltage of the silicon carbide substrate and the silicon substrate used in the second embodiment. Under the condition of leakage current of 1 mA / mm, the breakdown voltage of the silicon carbide substrate used in the second embodiment is 984V. In contrast, the breakdown voltage of the silicon substrate used in the second embodiment is 783V.

[0030] Therefore, as can be seen from Figures 7, 8 and 9, the use of silicon carbide substrates has higher drain current, higher current switching ratio and higher breakdown voltage compared to silicon substrates, thus exhibiting better switching characteristics and high voltage resistance.

[0031] Figure 10 shows the output characteristics of the second embodiment using a silicon carbide substrate and a silicon substrate at different temperatures. In the second embodiment, the output current attenuation rates of the silicon carbide substrate at temperatures of 300K, 350K, 400K, and 450K are 0%, 6.5%, 18.2%, and 27.8%, respectively, and their normalized on-resistances are 1, 1.09, 1.2, and 1.81, respectively. In contrast, the output current attenuation rates of the silicon substrate in the second embodiment at temperatures of 300K, 350K, 400K, and 450K are 0%, 14.3%, 22.7%, and 41.2%, respectively, and their normalized on-resistances are 1, 1.21, 1.37, and 1.71, respectively.

[0032] Therefore, as can be seen from Figure 10, the silicon carbide substrate used in the second embodiment has better thermal conductivity and heat dissipation than the silicon substrate, resulting in a smaller current decay rate in high-temperature environments and better heat resistance.

[0033] Figures 11 and 12 are waveform diagrams of the dual-pulse test using a silicon carbide substrate and a silicon substrate, respectively, in the second embodiment. The turn-on and turn-off times of the silicon carbide substrate in the second embodiment are 71 ns and 52 ns, respectively, with corresponding total energy losses of 17 μJ and 8.2 μJ. In contrast, the turn-on and turn-off times of the silicon substrate in the second embodiment are 103 ns and 191 ns, respectively, with corresponding total energy losses of 26 μJ and 14.9 μJ.

[0034] Therefore, as can be seen from Figures 11 and 12, the second embodiment using a silicon carbide substrate has a shorter turn-on and turn-off time and a smaller energy loss compared to a silicon substrate, thus exhibiting better switching characteristics.

[0035] In summary, the monolithic gallium nitride stacked transistor of the present invention, by providing a P-type doped gallium nitride layer 71 between the aluminum gallium nitride layer 4 and the enhancement gate conductive layer 72, indirectly changes the junction band characteristics of the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3, thereby blocking the formation of the two-dimensional electron gas 2DEG, so that the enhancement gate 7 has the characteristics of a normally off gate. Therefore, the series connection of the normally on GaN HEMT and the normally off GaN HEMT constitutes a monolithic gallium nitride stacked transistor with normally off characteristics. Since the first embodiment does not provide a fluorine ion implantation region, the crystal structure of the transistor will not be destroyed by high-energy ions. Compared with the conventional gallium nitride stacked transistors that form the enhancement gate with a fluorine ion implantation region, it has better electrical characteristics, and thus the purpose of the present invention is indeed achieved.

[0036] Furthermore, the transistor is composed of the normally open GaN HEMT and the normally closed GaN HEMT. Compared with the conventional stacked transistor composed of GaN HEMT and Si MOSFET, it has advantages such as high temperature resistance, reduced packaging complexity and reduced parasitic inductance.

[0037] However, the above description is only an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention. [Simplified Explanation of the Diagram]

[0038] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein:

[0039] Figure 1 is a schematic diagram of a conventional integrated gallium nitride stacked transistor.

[0040] Figure 2 is a circuit diagram of the first embodiment of the monolithic gallium nitride stacked transistor of the present invention.

[0041] Figure 3 is a schematic diagram of the first embodiment.

[0042] Figure 4 is a schematic diagram of the energy band of a depleted gate with one dielectric layer omitted.

[0043] Figure 5 is a schematic diagram of the energy band of an enhanced gate.

[0044] Figure 6 is a schematic diagram of the second embodiment of the monolithic gallium nitride stacked transistor of the present invention.

[0045] Figure 7 is a comparison of the transistor characteristic curves and external conduction of the silicon carbide substrate and the silicon substrate in the second embodiment.

[0046] Figure 8 is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate used in the second embodiment.

[0047] Figure 9 is a comparison diagram of the breakdown voltage of the silicon carbide substrate and the silicon substrate used in the second embodiment.

[0048] Figure 10 is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate at different temperatures in the second embodiment.

[0049] Figure 11 is a waveform diagram of a double-pulse test using a silicon carbide substrate in the second embodiment.

[0050] Figure 12 is a waveform diagram of a double-pulse test using a silicon substrate in the second embodiment.

Claims

1. A single-chip integrated gallium nitride stacked transistor, comprising: a substrate; a buffer layer disposed on the substrate; a gallium nitride channel layer disposed on the buffer layer; an aluminum gallium nitride layer disposed on the gallium nitride channel layer; a source electrode disposed on the aluminum gallium nitride layer; a drain electrode disposed on the aluminum gallium nitride layer; an enhancement-mode gate electrode located between the source electrode and the drain electrode and disposed on the aluminum gallium nitride layer, and including a p-type doped gallium nitride layer and an enhancement-mode gate conductive layer disposed on the p-type doped gallium nitride layer; a depletion-mode gate electrode located between the source electrode and the drain electrode and electrically connected to the source electrode, and disposed on the aluminum gallium nitride layer, and including a depletion-mode gate conductive layer; and a node electrode disposed on the aluminum gallium nitride layer, located between the enhancement-mode gate electrode and the depletion-mode gate electrode, and electrically connected to the depletion-mode gate electrode.

2. The monolithic gallium nitride stacked transistor as described in claim 1 further comprises a dielectric layer, wherein, The dielectric layer is located between the enhanced gate conductive layer and the P-type doped gallium nitride layer.

3. The monolithic gallium nitride stacked transistor as described in claim 1 further comprises a dielectric layer, wherein, The dielectric layer is located between the depleted gate conductive layer and the aluminum gallium nitride layer.

4. The monolithic gallium nitride stacked transistor as described in claim 1 further comprises a dielectric layer, wherein, The dielectric layer is located between the enhanced gate conductive layer and the aluminum gallium nitride layer, and between the depleted gate conductive layer and the aluminum gallium nitride layer.

5. The monolithically integrated gallium nitride stacked transistor as claimed in claim 1, wherein, The source electrode is embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

6. The monolithically integrated gallium nitride stacked transistor as claimed in claim 1, wherein, The drain is embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

7. The monolithic gallium nitride stacked transistor as described in claim 1 further comprises a source field plate, wherein, The source field plate is located at intervals on the side of the depleted gate away from the substrate and is electrically connected to the source.

8. The monolithic gallium nitride stacked transistor as claimed in claim 1, wherein, The substrate is selected from one of silicon substrate, silicon carbide substrate, sapphire substrate, or insulator silicon substrate.

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