Semiconductor structures and methods of forming the same

Abstract

In an embodiment, a method includes forming an upper gate structure adjacent to a first source / drain region and a second source / drain region and a lower gate structure adjacent to a third source / drain region; patterning a first opening and a second opening through a first dielectric layer to expose the first source / drain region and the second source / drain region; patterning to extend the second opening through a second dielectric layer to expose the third source / drain region; forming a protective layer over exposed surfaces of the first dielectric layer; forming a first epitaxial regrowth layer over the first source / drain region and a second epitaxial regrowth layer over the second source / drain region; removing the protective layer; forming a first source / drain contact to the first epitaxial regrowth layer; and forming a second source / drain contact to the second epitaxial regrowth layer and the third source / drain region.