Integrated circuit and method for forming the same

Abstract

A memory unit includes a first IO-functional circuit and a second IO-functional circuit separated by a padding area. Each of the first IO-functional circuit and the second IO-functional circuit is associated with an array of bit-cells. The first IO-functional circuit has transistors in a first group of first-type active-region structures and in a first group of second-type active-region structures. The second IO-functional circuit has transistors in a second group of first-type active-region structures and in a second group of second-type active-region structures. The padding area includes a third group of first-type active-region structures which is adjacent to the first group of first-type active-region structures and adjacent to the second group of first-type active-region structures.