Semiconductor device and methods of formation

Abstract

A top electrode layer of a capacitor structure of a pixel sensor is connected to a bottom contact of an interconnect layer of a semiconductor device. The bottom contact is located at the bottom of the capacitor structure and connects the top electrode layer to a reset voltage source and to a reset transistor of the pixel sensor without the use of additional vias, metallization layers, and / or other conductive interconnect structures that extend alongside the capacitor structure. As a result, the lateral footprint of the capacitor structure can be increased, which increases capacitor area of the capacitor structure.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to an apparatus and method, and more specifically, to a semiconductor device and a method for forming the same. [Previous Technology]

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors arranged in an array of pixel sensors. Each pixel sensor of a CMOS image sensor may include a photodiode configured to convert photons of incident light into a photocurrent of electrons. The magnitude of the photocurrent is at least partially based on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array are capable of sensing incident light over a wide range of intensities, the images and / or videos produced by the CMOS image sensor can achieve a high range of brightness and contrast. [Summary of the Invention]

[0003] According to some embodiments, a semiconductor device includes one or more dielectric layers, a capacitor structure, a first bottom contact, and a second bottom contact. The capacitor structure is located in the one or more dielectric layers and includes one or more trench structures, a first electrode layer, an insulating layer, and a second electrode layer. The first electrode layer is located in the one or more trench structures. The insulating layer is located on the first electrode layer in the one or more trench structures. The second electrode layer is located on the insulating layer in the one or more trench structures. The first bottom contact is located below the one or more trench structures along a first direction, wherein the first electrode layer is electrically connected to the first bottom contact. The second bottom contact is laterally adjacent to one side of the first bottom contact in a second direction perpendicular to the first direction, wherein the second electrode layer is electrically connected to the second bottom contact, and wherein at least a portion of the second electrode layer is located above the second bottom contact.

[0004] According to some embodiments, a method of forming a semiconductor device includes: forming a first bottom contact in a dielectric layer; forming a second bottom contact in the dielectric layer, wherein the second bottom contact is adjacent to and spaced apart from the first bottom contact; forming a first trench above the first bottom contact, wherein the top surface of the first bottom contact is exposed at the bottom of the first trench; forming a first electrode layer of a capacitor structure on the top surface of the first bottom contact in the first trench; forming a second trench above the second bottom contact; forming an insulating layer of the capacitor structure in the first trench and the second trench, wherein the insulating layer is located on the first electrode layer in the first trench and on the bottom surface of the second trench; removing a portion of the insulating layer and a portion of the bottom surface of the second trench to expose the top surface of the second bottom contact; and forming a second electrode layer of the capacitor structure on the insulating layer in the first trench and the second trench, wherein a portion of the second electrode layer is formed on the top surface of the second bottom contact.

[0005] According to some embodiments, a semiconductor device includes a capacitor structure, a first bottom contact, and a second bottom contact. The capacitor structure includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer is located on the sidewalls and bottom surface of a trench structure. The second conductive layer is located in the trench structure. The insulating layer is located between the first conductive layer and the second conductive layer. The first bottom contact is located below the bottom surface of the trench structure, wherein the first conductive layer is located on the first bottom contact. The second bottom contact is laterally adjacent to the first bottom contact, wherein the second conductive layer is located on the second bottom contact.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing the first and second features from being in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and not to imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship or characteristics of one element or feature to another, as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] In some cases, the number of incident photons that a pixel sensor can absorb before reaching saturation may be limited. "Saturation" refers to the degree of photon absorption beyond which the pixel sensor can no longer absorb additional photons. Saturation of a pixel sensor will result in a limited dynamic range because it cannot obtain additional brightness and color information from further photon absorption.

[0009] The amount of photocurrent charge that a pixel sensor can store before reaching saturation is called the full well capacity (FWC) of the pixel sensor. The full well capacity of a pixel sensor can be based at least in part on the dimensions (e.g., depth, width, volume) and / or the shape of the photodiode. While increasing the size of the photodiode can increase the full well capacity of the pixel sensor, doing so may come at the cost of reducing the pixel sensor density in the pixel sensor array, which may reduce the resolution of the pixel sensor array.

[0010] To increase the full-well capacity of a pixel sensor, an image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device) may include a capacitor structure configured to store charge associated with the photocurrent generated by the pixel sensor before the charge is transferred to a floating diffusion node associated with the pixel sensor. The photocurrent can be transferred from the pixel sensor to the capacitor structure, allowing the pixel sensor to generate more charge for the photocurrent instead of storing the photocurrent entirely in the photodiode and / or floating diffusion node. Therefore, the capacitor structure can increase the full-well capacity of the pixel sensor, which may enable the image and / or video generated by the pixel sensor array to achieve a higher range of brightness and / or contrast (e.g., high dynamic range, HDR). The capacitor structure is designed to achieve a small lateral footprint and may include a metal-insulator-metal (MIM) stack, wherein the bottom electrode layer and the top electrode layer are arranged alternately and separated by an insulating layer.

[0011] The pixel sensor may be a lateral overflow integration capacitor (LOFIC) pixel sensor, which includes an overflow gate and an overflow capacitor including a capacitor structure. The overflow capacitor may be electrically coupled to a floating diffusion node through the overflow gate, allowing photocurrent to be transferred from the floating diffusion node to the overflow capacitor for temporary storage. A reset gate may be used to remove or discharge the photocurrent in the floating diffusion node and / or the overflow capacitor by applying a reset voltage to the floating diffusion node and / or the overflow capacitor, thereby "resetting" the floating diffusion node and / or the overflow capacitor (e.g., by draining any residual charge in the floating diffusion node and / or the overflow capacitor).

[0012] The capacitor structure of the Lateral Overflow Integrated Capacitor (LOFIC) pixel sensor may be included in the interconnect layer of the semiconductor device (e.g., a back end of line (BEOL) region). Vias, metallization layers, contacts, and / or other conductive structures in the interconnect layer may connect the capacitor structure to one or more transistors of the LOFIC pixel sensor located in the bottom device layer of the semiconductor device (e.g., a front end of line (FEOL) region). To connect the top electrode layer of the capacitor structure to the transistors of the LOFIC pixel sensor, a top connection to the top electrode layer may be formed on top of the capacitor structure, and additional vias, metallization layers, and / or other conductive interconnect structures extending adjacent to the capacitor structure may connect the top connection to the transistors.

[0013] The top connection and additional vias, metallization layers, and / or other conductive interconnects extending alongside the capacitor structure limit the size of the capacitor structure, and therefore also limit its capacitance, as these structures restrict the lateral dimensions of the capacitor structure. As a result, the limited capacitance of the capacitor structure may be insufficient to achieve the high dynamic range (HDR) of the pixel sensor.

[0014] Furthermore, forming top connections may damage the top electrode layer, for example, during the etching process that forms the grooves for the top connections. In particular, plasma-based etching may be performed, which may cause the top electrode layer to be damaged by plasma charges.

[0015] Furthermore, the capacitor structure in the pixel sensor array may be connected to a reset voltage source on a per-pixel basis. This results in further additional conductive wiring in the interconnect layer, increasing the time required to reset the capacitor structure (e.g., due to the increase in the resistor-capacitor (RC) time constant of the capacitor structure), thereby reducing the operating speed of the pixel sensor array and the frame rate (e.g., frames per second, FPS) of the pixel sensor array.

[0016] In some embodiments described herein, the top electrode layer of the capacitor structure of the pixel sensor (e.g., a LOFIC pixel sensor) is connected to a bottom contact (e.g., relative to a top connection) of the semiconductor device interconnect layer. The bottom contact is located at the bottom of the capacitor structure and connects the top electrode layer to the reset voltage source and the reset transistor of the pixel sensor, without the need for additional vias, metallization layers, and / or other conductive interconnect structures extending alongside the capacitor structure. As a result, the lateral footprint of the capacitor structure can be increased, thereby increasing the capacitance area of ​​the capacitor structure.

[0017] Using bottom contacts also prevents the top electrode layer from being damaged by plasma charges, because the top electrode layer is formed on the bottom contacts, rather than forming the top connection on the top electrode layer. Therefore, plasma charge damage that may occur during the etching process that forms the top connection trench is avoided. Connecting the top electrode layer to the bottom contacts also helps to enable local reset functionality for pixel sensors and other pixel sensors in a pixel sensor array within a semiconductor device. For example, the bottom connection may be part of an existing metallization loop or an additional metallization layer for connecting the capacitor structure of the pixel sensor to a reset voltage source, allowing the capacitor structure to be locally reset with a reduced RC time constant, resulting in faster capacitor reset speeds and higher frame rates compared to other pixel sensor arrays. In some embodiments, in addition to providing a bottom contact structure, capacitance is further increased by using a trench capacitor structure with a second metal-insulator-metal structure on a first metal-insulator-metal structure.

[0018] Figures 1A and 1B are diagrams of an example semiconductor device 100 described herein. Semiconductor device 100 may include a system-on-chip (SoC) device, logic devices such as a central processing unit (CPU) or graphics processing unit (GPU), memory devices (e.g., high bandwidth memory (HBM) devices), image sensor devices (e.g., complementary metal-oxide-semiconductor (CMOS) image sensor devices), and / or other types of semiconductor devices.

[0019] Figures 1A and 1B show cross-sectional views of a semiconductor device 100. As shown in Figures 1A and 1B, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104, arranged in the z-direction relative to the device layer 102 in the semiconductor device 100. For example, the interconnect layer 104 may be located above the device layer 102. As another example, the interconnect layer 104 may be located below the device layer 102.

[0020] Device layer 102 may also be referred to as the front end of line (FEOL) region of semiconductor device 100. Interconnect layer 104 may also be referred to as the back end of line (BEOL) region of semiconductor device 100 and may include conductive structures for transmitting signals and / or providing power distribution throughout semiconductor device 100. In some embodiments, semiconductor device 100 includes interconnect layers 104 located above and below device layer 102. A first interconnect layer 104 located on a first side of device layer 102 may be used for signal propagation throughout semiconductor device 100, while a second interconnect layer 104 located on a second side of device layer 102 may be used for power distribution of semiconductor device 100.

[0021] Device layer 102 includes a substrate 106 of semiconductor device 100. Substrate 106 may correspond to a portion of a semiconductor wafer forming semiconductor device 100. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrate. Substrate 106 may extend in semiconductor device 100 along the x-direction and / or y-direction such that the top and bottom surfaces of substrate 106 are substantially perpendicular to the z-direction in semiconductor device 100.

[0022] The integrated circuit device 108 may be contained in and / or on the substrate 106 of the device layer 102 of the semiconductor device 100. The integrated circuit device 108 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (FinFET) structures, front-end gate all around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices.

[0023] The front-end transistor structure may include multiple source / drain regions that may correspond to doped regions of the substrate 106 and are separated by channel regions in the substrate 106. In some embodiments, the source / drain regions are doped with a first type of dopant (e.g., p-type dopant such as boron (B) and / or gallium (Ga), n-type dopant such as phosphorus (P) and / or arsenic (As)), while the channel regions are doped with a second type of dopant different from the first type of dopant. The front-end transistor structure may include a gate structure located above and / or around the channel regions. The gate dielectric layer of the front-end transistor structure may be located between the gate structure and the channel regions. The gate structure may include a polysilicon gate, a metal gate having a high-k gate dielectric layer such as hafnium oxide (HfOx, such as HfO2), and / or other types of gate structures.

[0024] A dielectric layer 110 is contained above a substrate 106. The dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 110 includes a dielectric material that allows portions of the substrate 106 and / or the integrated circuit device 108 to be selectively etched or etch-free, and / or electrically isolates the integrated circuit device 108 in the device layer 102. The dielectric layer 110 includes silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 110 may extend in the semiconductor device 100 along the x-direction and / or y-direction. A contact 112 (e.g., a source / drain contact, a gate contact) may pass through the dielectric layer 110 and be located between the integrated circuit device 108 and the interconnect layer 104. Contact 112 can electrically connect integrated circuit device 108 to interconnect layer 104. Contact 112 may include vias, plugs, and / or other types of elongated conductive structures. Contact 112 may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al) and / or gold (Au), as well as other conductive materials.

[0025] Interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged along a direction generally perpendicular to the top surface of substrate 106 (e.g., the z-direction). The dielectric layers may include interlayer dielectric layers 114 and etch stop layers 116, which are arranged alternately along the z-direction. Interlayer dielectric layers 114 and etch stop layers 116 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0026] The interlayer dielectric layer 114 may each comprise a low-k oxide material, such as silica (SiOx) or undoped silicate glass (USG). Additionally and / or alternatively, the interlayer dielectric layer 114 may each comprise boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 114 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of dielectric materials with extremely low dielectric constants include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), poly(p-xylene), bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx), among others.

[0027] The etch stop layers 116 may each comprise silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 114 and the etch stop layers 116 comprise different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 104. For example, the interlayer dielectric layer 114 may each comprise a low-k dielectric material, such as undoped silicate glass (USG), while the etch stop layers 116 may each comprise a high-k dielectric material, such as silicon nitride (SixNy) or silicon carbide (SiC). Furthermore, and / or alternatively, the two or more etch stop layers 116 may comprise different materials. For example, one or more first etch stop layers 116 may comprise silicon nitride (SixNy), while one or more second etch stop layers 116 may comprise silicon carbide (SiC).

[0028] Interconnect layer 104 includes a plurality of conductive structures arranged in multiple layers. The conductive structures may be electrically coupled and / or physically coupled to one or more integrated circuit devices 108 in device layer 102. The conductive structures provide electrical wiring to enable signals and / or power to be supplied to and / or from integrated circuit devices 108.

[0029] The conductive structure may include multiple layers 118a, 118b, 118c, 118d, 118e that are vertically arranged in the z-direction (e.g., vertically alternating) and alternate with multiple layers 120a, 120b, 120c, 120d. Each of layers 118a, 118b, 118c, 118d, 118e includes a metallization structure 122, while each of layers 120a, 120b, 120c, 120d includes an interconnection structure 124.

[0030] Layers 118a, 118b, 118c, 118d, and 118e of the metallization structure 122 may be referred to as M layers. For example, layer 118a of the metallization structure 122 (referred to as the metal-0 (M0) layer) may be located at the bottom of the interconnect layer 104 and may be coupled to the device layer 102. In particular, the metallization structure 122 in the M0 layer may be coupled to the contact 112 of the integrated circuit device 108 in the device layer 102 (e.g., the contact layer referred to as the "CO" layer). Layer 118b of the metallization structure 122 (referred to as the metal-1 (M1) layer) may be located above layer 118a of the metallization structure 122 in the interconnect layer 104, and layer 118c of the metallization structure 122 (referred to as the metal-2 (M2) layer) may be located above layer 118b of the metallization structure 122, and so on.

[0031] Layer 120a of interconnect structure 124 (referred to as via-1 (V0) layer) may be included between M0 layer and M1 layer to interconnect M0 layer and M1 layer, and layer 120b of interconnect structure 124 (referred to as via-2 (V1) layer) may be included between M1 layer and M2 layer to interconnect M1 layer and M2 layer, and so on.

[0032] The metallization structure 122 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. The interconnect structure 124 may include vias, interconnects, and / or combinations of other types of conductive structures. The metallization structure 122 and the interconnect structure 124 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, one or more pad layers are included between the dielectric layer of the interconnect layer 104 and the metallization structure 122, and / or between the dielectric layer of the interconnect layer 104 and the interconnect structure 124. The one or more pad layers may include barrier pads, adhesive pads, and / or other types of pads. Examples of materials for the one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as other examples.

[0033] In some embodiments, the topmost conductive structure (e.g., the topmost metallization structure 122, the topmost interconnect structure 124) may be coupled to a connection structure on top of the semiconductor device 100. The connection structure may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under-bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures. In some embodiments, the topmost conductive structure (e.g., the topmost metallization structure 122, the topmost interconnect structure 124) may be coupled to a bonding structure, such as bonding pads and / or bonding vias.

[0034] As further shown in FIG1A, a trench capacitor structure 126a is included in the interconnect layer 104 of the semiconductor device 100, and as further shown in FIG1B, a trench capacitor structure 126b is included in the interconnect layer 104 of the semiconductor device 100. The trench capacitor structures 126a and 126b may extend through and / or be included in one or more dielectric layers in the interconnect layer 104, such as one or more interlayer dielectric layers 114 and / or one or more etch stop layers 116. In some embodiments, integrated circuit devices 108 are electrically coupled to the trench capacitor structure 126a or the trench capacitor structure 126b to form memory cells (e.g., dynamic random access memory (DRAM) cells or other capacitor-based memory cells) in the semiconductor device 100. In some embodiments, the trench capacitor structure 126a or the trench capacitor structure 126b is configured to provide charge decoupling for one or more integrated circuit devices 108. In some embodiments, trench capacitor structure 126a or trench capacitor structure 126b is configured to store charge (e.g., photocurrent) of integrated circuit device 108 (e.g., pixel sensor) in semiconductor device 100. In some embodiments, trench capacitor structure 126a or trench capacitor structure 126b is configured to perform another function in semiconductor device 100.

[0035] The trench capacitor structures 126a and 126b may be electrically and / or physically coupled to a first bottom contact 128 and a second bottom contact 130 at their bottoms. The first bottom contact 128 and the second bottom contact 130 may each include one or more conductive structures in the interconnect layer 104, such as one or more metallization structures 122 and / or one or more interconnect structures 124, etc. In some embodiments, the trench capacitor structure may be electrically and / or physically coupled to a top contact. For example, referring to FIG1B, the trench capacitor structure 126b is coupled to the metallization structure 122 (e.g., the top contact) via the interconnect structure 124.

[0036] As described above, Figures 1A and 1B are provided as examples. Other examples may differ from those described with respect to Figures 1A and 1B.

[0037] Figures 2A to 2T are diagrams of an example embodiment 200 forming the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing tools may be used to perform one or more semiconductor processing operations associated with Figures 2A to 2T, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0038] Referring to FIG2A, when forming trench capacitor structures 126a and 126b, one or more trenches 202 are formed above the first bottom contact 128. The first bottom contact 128 and the second bottom contact 130 may be contained in an interlayer dielectric layer 114a in the interconnect layer 104 of the semiconductor device 100, and the top surfaces of the first bottom contact 128 and the second bottom contact 130 may be coplanar or substantially coplanar with each other. Initially, the trenches 202 of the trench capacitor structures 126a and 126b may extend through one or more dielectric layers in the interconnect layer 104 of the semiconductor device 100, including through the interlayer dielectric layer 114b, etch stop layer 116b, interlayer dielectric layer 114c, etch stop layer 116c, and / or interlayer dielectric layer 114d, etc. In some embodiments, trench 202 may have a high aspect ratio, that is, the ratio of the depth (or height) of trench 202 to its lateral width (or critical dimension). Therefore, trench capacitor structures 126a and 126b may be referred to as deep trench capacitor (DTC) structures. In some embodiments, the aspect ratio of trench 202 may be approximately 10:1 or greater. In some embodiments, trench 202 may have an aspect ratio falling within the range of approximately 20:1 to approximately 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0039] Figure 2B is a cross-sectional view along line AA in the top view of Figure 2C. As shown in Figures 2B and 2C, a protective conductive layer 132 can be deposited on the sidewalls and bottom surface of the trench 202. The bottom surface of the trench 202 corresponds to the top surface of the etch stop layer 116a, so the protective conductive layer 132 can be in physical contact with the top surface of the etch stop layer 116a. The protective conductive layer 132 can also be deposited on the top surface of the interlayer dielectric layer 114d between and / or next to adjacent trenches 202, so that the protective conductive layer 132 can be in physical contact with the top surface of the interlayer dielectric layer 114d. In some embodiments, the protective conductive layer 132 is conformally deposited using a deposition tool so that the protective conductive layer 132 conforms to the contour of the trench 202. In some embodiments, conformal chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) techniques are used to deposit the protective conductive layer 132. Examples of materials for the protective conductive layer 132 include tantalum nitride (TaN), titanium nitride (TiN), aluminum (Al), and / or tungsten (W). As shown in FIG2C, the semiconductor device 100 may include an array of trenches 202.

[0040] Figure 2D is a cross-sectional view along line BB in the top view of Figure 2E. As shown in Figures 2D and 2E, a horizontal portion (extending along the x-direction) of the protective conductive layer 132 on the top surface of the interlayer dielectric layer 114d in trench 202 is removed using a directional reactive ion etching (RIE) process, in which gas etchants such as oxygen (O2), argon (Ar), and / or fluorine-containing gases can be used. Fluorine-containing etchants may include carbon-fluorine based (CFx) gas etchants, such as carbon tetrafluoride (CF4) gas etchants. As shown in Figure 2D, the reactive ion etching (RIE) process also removes a portion of the etch stop layer 116a to deepen trench 202, exposing a portion of the top surface of the first bottom contact 128. The remaining portion of the protective conductive layer 132 lies on a portion of the top surface of the remaining portion of the etch stop layer 116a.

[0041] Figure 2F is a cross-sectional view along line CC in the top view of Figure 2G. As shown in Figures 2F and 2G, a bottom electrode layer 134 can be deposited on the sidewalls and bottom surface of the trench 202. The bottom surface of the trench 202 corresponds to the top surface of the first bottom contact 128, so the bottom electrode layer 134 can be in physical contact with the top surface of the first bottom contact 128. The sidewalls of the trench 202 correspond to the sides of the protective conductive layer 132, so the bottom electrode layer 134 can be in physical contact with the sides of the protective conductive layer 132. The bottom electrode layer 134 can also be deposited on the top surface of the interlayer dielectric layer 114d and the top surface of the protective conductive layer 132 between and / or next to adjacent trenches 202, so that the bottom electrode layer 134 can be in physical contact with the top surfaces of the interlayer dielectric layer 114d and the protective conductive layer 132. In some embodiments, the bottom electrode layer 134 is conformally deposited using a deposition tool so that the bottom electrode layer 134 conforms to the contour of the trench 202. In some embodiments, conformal chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) techniques are used to deposit the bottom electrode layer 134.

[0042] In some embodiments, a barrier layer may be deposited on the sidewalls and bottom surface of the trench 202 prior to the deposition of the bottom electrode layer 134. In this case, the barrier layer may be in physical contact with the top surface of the first bottom contact 128 and with the side surface of the protective conductive layer 132. The barrier layer may also be deposited between and / or next to the top surface of the interlayer dielectric layer 114d and the protective conductive layer 132, such that the barrier layer is in physical contact with the top surfaces of the interlayer dielectric layer 114d and the protective conductive layer 132. In some embodiments, the barrier layer is conformally deposited using a deposition tool to conform to the contour of the trench 202. In some embodiments, the barrier layer is deposited using conformal chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) techniques. The barrier layer prevents conductive material (e.g., copper (Cu)) of the first bottom contact 128 from migrating upward into the bottom electrode layer 134 and may include tantalum (Ta), tantalum nitride (TaN), and / or other suitable barrier materials. Regardless of whether there is a barrier layer, the bottom electrode layer 134 is electrically connected to the first bottom contact 128.

[0043] Figure 2H is a cross-sectional view of line DD in the top view of Figure 2I. As shown in Figures 2H and 2I, photoresist layer 204 is deposited in trench 202 and on the top surface of bottom electrode layer 134. In some embodiments, a deposition tool can be used to form photoresist layer 204 in trench 202 and on the top surface of bottom electrode layer 134. An exposure tool can be used to expose photoresist layer 204 to a radiation source to pattern photoresist layer 204. A development tool can be used to develop and remove portions of photoresist layer 204 to expose the pattern as shown in Figure 2H.

[0044] Figure 2J is a cross-sectional view of line EE in the top view of Figure 2K. As shown in Figures 2J and 2K, the pattern in the photoresist layer 204 is used to etch the exposed portion of the bottom electrode layer 134 and the bottom portion of the interlayer dielectric layers 114b, 114c, 114d and the etch stop layers 116b, 116c to form additional trenches 206, 208. The exposed portion of the bottom electrode layer 134 and the bottom portion of the interlayer dielectric layers 114b, 114c, 114d and the etch stop layers 116b, 116c can be etched according to the pattern using an etching tool to form additional trenches 206, 208. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer 204 can be removed using a photoresist removal tool (e.g., using chemical stripping agents, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to etch the exposed portion of the bottom electrode layer 134 and the bottom portion of the interlayer dielectric layers 114b, 114c, 114d and the etch stop layers 116b, 116c according to the pattern to form additional trenches 206, 208.

[0045] After the etching operation and removal of the remaining portion of the photoresist layer 204, a portion of the bottom electrode layer 134 remains in the trench 202 and on the top surface of the interlayer dielectric layer 114d. Furthermore, a protective conductive layer 132 remains on the opposite side surfaces of the remaining portion of the bottom electrode layer 134 in the trench 202. The remaining portion of the protective conductive layer 132 supports the portion of the bottom electrode layer 134 in the trench 202 to prevent the portion of the bottom electrode layer 134 in the trench 202 from collapsing after the etching operation and removal of the remaining portion of the photoresist layer 204. The remaining portion of the protective conductive layer 132 also protects (e.g., covers) the sidewalls of the bottom electrode layer 134 during the etching operation and any subsequent cleaning steps. For example, a wet cleaning operation used to remove the etching polymer used during the etching operation may damage exposed portions of the bottom electrode layer 134. The protective conductive layer 132 prevents the bottom electrode layer 134 from being exposed to chemicals used during the wet cleaning operation.

[0046] In some embodiments, the thickness of the remaining portion of the protective conductive layer 132 may range from about 100 angstroms to about 1000 angstroms. However, other values ​​and ranges are also within the scope of this disclosure. A thickness of less than about 100 angstroms for the remaining portion of the protective conductive layer 132 may result in a lack of support and / or protection against wet cleaning chemicals for the remaining portion of the bottom electrode layer 134 in trench 202. A thickness of more than about 1000 angstroms for the remaining portion of the protective conductive layer 132 may result in difficulties (e.g., lack of sufficient space) in forming the remaining layers of trench capacitor structures 126a and / or 126b in the additional trenches 206, 208.

[0047] The trenches 202, 206, and / or 208 of the trench capacitor structures 126a and / or 126b may pass through one or more dielectric layers in the interconnect layer 104 of the semiconductor device 100, including through etch stop layer 116a, interlayer dielectric layer 114a, etch stop layer 116b, interlayer dielectric layer 114c, etch stop layer 116c, and / or interlayer dielectric layer 114d, and other examples. In some embodiments, the trenches of the trench capacitor structures 126a and / or 126b may have a high aspect ratio, i.e., the ratio of the depth (or height) of the trench to the lateral width (or critical dimension) of the trench. Therefore, the trench capacitor structures 126a and / or 126b may be referred to as deep trench capacitor (DTC) structures. In some embodiments, the aspect ratio of the trenches 202, 206, and / or 208 may be approximately 10:1 or greater. In some embodiments, ditches 202, 206, and / or 208 may have a depth-to-width ratio ranging from about 20:1 to about 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0048] As shown in FIG2L, an insulating layer 136 may be deposited on the sidewalls and bottom surfaces of trenches 206 and 208, and on the exposed surface of the bottom electrode layer 134 in trench 202. The bottom surfaces of trenches 206 and 208 correspond to the top surface of etch stop layer 116a, so the insulating layer 136 may be in physical contact with the top surface of etch stop layer 116a. A portion or each sidewall of trenches 206 and 208 may correspond to the side surface of protective conductive layer 132, so the insulating layer 136 may be in physical contact with the side surface of protective conductive layer 132. The insulating layer 136 may also be deposited on the top surface of the remaining portion of the bottom electrode layer 134 on the interlayer dielectric layer 114d, and on the top surface of the portions of the bottom electrode layer 134 and protective conductive layer 132 between and / or next to adjacent trenches 202, 206, 208, such that the insulating layer 136 may be in physical contact with the top surface of the bottom electrode layer 134 and protective conductive layer 132. In some embodiments, an insulating layer 136 is conformally deposited using a deposition tool to conform to the contours of trenches 202, 206, and 208. In some embodiments, the insulating layer 136 is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques.

[0049] The insulating layer 136 may include one or more electrically insulating materials. In some embodiments, the insulating layer 136 includes one or more low-k dielectric materials, such as silicon oxide (SiOx, e.g., SiO2). Additionally and / or alternatively, the insulating layer 136 may include one or more high-k dielectric materials, such as zirconium oxide (ZrOx, e.g., ZrO2), aluminum oxide (AlxOy, e.g., Al2O3), silicon nitride (SixNy, e.g., Si3N4), yttrium oxide (YxOy, e.g., Y2O3), lanthanum oxide (LaxOy, e.g., La2O3), and / or hafnium oxide (HfOx, e.g., HfO2). In some embodiments, the insulating layer 136 is a multilayer stack comprising multiple dielectric layers. For example, the insulating layer 136 may include a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0050] As further shown in FIG2L, the conductive layer 138 may be deposited on the exposed surface of the insulating layer 136 in trenches 202, 206, 208. The conductive layer 138 may also be deposited on the top surface of the insulating layer 136 on the interlayer dielectric layer 114d and on the top surface of the insulating layer 136 between and / or adjacent to trenches 202, 206, 208. In some embodiments, the conductive layer 138 is conformally deposited using a deposition tool to conform to the contours of trenches 202, 206, 208. In some embodiments, conformal chemical vapor deposition and / or atomic layer deposition techniques are used to deposit the conductive layer 138. The conductive layer 138 may include titanium nitride (TiN) and / or other suitable conductive materials.

[0051] As shown in Figure 2M, a bottom anti-reflective coating (BARC) 210 is deposited in trenches 202, 206, and 208, and then a photoresist layer 212 is deposited on the bottom anti-reflective coating 210. A pattern 214 can be formed in the photoresist layer 212. The bottom anti-reflective coating 210 can be deposited in trenches 202, 206, and 208 using a deposition tool, and the photoresist layer 212 can be formed on the bottom anti-reflective coating 210 (e.g., using spin coating or other suitable deposition techniques). The photoresist layer 212 can be exposed to a radiation source using an exposure tool to pattern the photoresist layer 212. A developing tool can be used to develop and remove portions of the photoresist layer 212 to expose the pattern 214.

[0052] As shown in FIG. 2N, an etching tool can be used to etch the bottom portion of the bottom antireflective coating 210 and the insulating layer 136 and conductive layer 138 based on the pattern 214 in the photoresist layer 212 to create an opening 216 exposing the top surface portion of the second bottom contact 130. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. Gas etchants, such as oxygen (O2), argon (Ar), and / or fluorine-containing gases, can be used. Fluorine-containing etchants may include carbon-fluorine based (CFx) gas etchants, such as carbon tetrafluoride (CF4) gas etchants. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0053] As shown in FIG20, a top electrode layer 140 may be deposited on the exposed surface of the conductive layer 138 in trenches 202, 206, and 208, and on the exposed portion of the top surface of the second bottom contact 130 in trench 208. A portion of the top electrode layer 140 is formed on the second bottom contact 130 and may be in physical contact with the second bottom contact 130. Due to the deposition of the top electrode layer 140, trench structures 218, 220, and 222 corresponding to trenches 202, 206, and 208 are formed, respectively. Each of the trench structures 218, 220, and 222 includes a plurality of conformal layers conforming to the contours of trenches 202, 206, and 208. In trench structure 218, the conformal layer may include a bottom electrode layer 134, an insulating layer 136 located on the bottom electrode layer 134, and a conductive layer 138 located on the insulating layer 136. In trench structures 220 and 222, the conformal layer may include an insulating layer 136 and a conductive layer 138 located on the insulating layer 136. Trench structures 220 and 222 do not include a bottom electrode layer 134. The bottom electrode layer 134, the insulating layer 136, and the conductive layer 138 may each conform to the contour of trench 202 such that the bottom electrode layer 134, the insulating layer 136, and the conductive layer 138 conform to (e.g., along) the sidewalls and bottom surface of trench 202. Except for the exposed top surface of the second bottom contact 130 in trench 208, the insulating layer 136 and the conductive layer 138 may each conform to the contour of trenches 206 and 208 such that the insulating layer 136 and the conductive layer 138 conform to (e.g., along) the sidewalls and bottom surface of trenches 206 and 208. Trench capacitor structure 126a also includes a top electrode layer 140 located on the conductive layer 138 and on the exposed portion of the top surface of the second bottom contact 130. In some embodiments, the top electrode layer 140 is a filler layer that fills the remaining areas of trenches 202, 206.

[0054] As shown in Figure 2P, in trench 208, the top electrode layer 140 is a conformal layer conforming to the sidewalls and bottom surface of trench 208, and the dielectric plug layer 142 is further included in the remaining region of trench 208. The dielectric plug layer 142 may be, for example, an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric plug layer 142 may be deposited on the top electrode layer 140 using deposition tools via physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques.

[0055] As shown in FIG2Q, in some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, can be performed using a planarization tool to planarize the dielectric plug layer 142 after deposition. Alternatively, a bulk etching operation can be performed to reduce the thickness of the dielectric plug layer 142 in the z-direction.

[0056] The bottom electrode layer 134, the insulating layer 136, and the top electrode layer 140 correspond to the metal-insulator-metal (MIM) structure of the trench capacitor structure 126a. Therefore, the trench capacitor structure 126a can also be referred to as a MIM capacitor structure. The bottom electrode layer 134 (also called capacitor bottom metal (CBM)) and the top electrode layer 140 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive metal-containing materials, one or more conductive ceramic materials, and / or other types of conductive materials. For example, these include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 134 and the top electrode layer 140 include the same material or the same material composition. In some embodiments, the bottom electrode layer 134 and the top electrode layer 140 include different materials or different material compositions.

[0057] In some embodiments, a barrier layer may be deposited on the exposed surfaces of the conductive layer 138 in trenches 202, 206, 208, and on the exposed portion of the top surface of the second bottom contact 130 in trench 208, prior to the deposition of the top electrode layer 140. In this case, the barrier layer may be in physical contact with the top surface of the second bottom contact 130. In some embodiments, the barrier layer is conformally deposited using a deposition tool to conform to the contours of trenches 202, 206, 208. In some embodiments, the barrier layer is deposited using conformal chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) techniques. The barrier layer prevents conductive material (e.g., copper (Cu)) of the second bottom contact 130 from migrating upwards into the top electrode layer 140 and may include tantalum (Ta), tantalum nitride (TaN), and / or other suitable barrier materials. Regardless of the presence or absence of a barrier layer, the top electrode layer 140 is electrically connected to the second bottom contact 130.

[0058] FIG2R is a cross-sectional view of line FF in the top view of FIG2S. As shown in FIG2R and 2S, the sides of the dielectric plug layer 142, top electrode layer 140, conductive layer 138, insulating layer 136, bottom electrode layer 134, and interlayer dielectric layer 114d are removed to form a patterned trench capacitor structure 126a. The removal results in the formation of stage portions 224 at the locations where the sides of the dielectric plug layer 142, top electrode layer 140, conductive layer 138, insulating layer 136, bottom electrode layer 134, and interlayer dielectric layer 114d are removed. In some embodiments, a photomask layer is formed on a portion of the dielectric plug layer 142, and an etching operation is performed to etch the portions not covered by the photomask layer. The etching operation may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. Gas etchants such as oxygen (O2), argon (Ar), and / or fluorine-containing gases may be used. Fluorinated etchants may include fluorinated hydrocarbon (CFx) gas etchants, such as carbon tetrafluoride (CF4) gas etchants.

[0059] As shown in FIG2T, metallization structures 144, 146, 148 and interconnection structures (e.g., vias) 150, 152 are formed in a peripheral region 154 laterally adjacent to the trench capacitor structure 126a in the x-direction, and metallization structure 156 is formed on the trench capacitor structure 126a in the z-direction. Additional portions of the interlayer dielectric layer 114d are deposited using one or more deposition tools to increase the vertical height of the interlayer dielectric layer 114d in the z-direction, and etch stop layers 116d and 114e are deposited. In this way, the interlayer dielectric layer 114 and etch stop layer 116 can be aligned along the z-direction in the semiconductor device 100. Each interlayer dielectric layer 114 and each etch stop layer 116 can be deposited using one or more deposition tools employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some implementations, a planarization tool may be used to planarize the interlayer dielectric layer 114 and / or the etch stop layer 116 after depositing the interlayer dielectric layer 114 and / or etching the stop layer 116.

[0060] As further shown in FIG2T, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form metallization structures 144, 146, 148, 156 and interconnect structures 150, 152. In some embodiments, the first bottom contact 128, the second bottom contact 130, the metallization structures 144, 146, 148, 156, and the interconnect structures 150, 152 may be formed in multiple layers. For example, an interlayer dielectric layer 114 and an etch stop layer 116 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through the interlayer dielectric layer 114 and the etch stop layer 116 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a layer including a first bottom contact 128, a second bottom contact 130, and a metallization structure 144 (e.g., an M0 layer) may be formed in the interlayer dielectric layer 114a and the etch stop layer 116a (e.g., using one or more deposition tools and / or one or more planarization tools). Another interlayer dielectric layer 114b and another etch stop layer 116b may be formed, and a layer including an interconnect structure 150 (e.g., a V0 layer) may be formed in the interlayer dielectric layer 114b and the etch stop layer 116b. The remaining layers may be formed in a similar manner.

[0061] One or more deposition tools may be used to deposit metallized structures 144, 146, 148, 156, interconnect structures 150, 152, first bottom contacts 128, and / or second bottom contacts 130 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, after depositing metallized structures 144, 146, 148, 156, interconnect structures 150, 152, first bottom contacts 128, and / or second bottom contacts 130, a planarization tool may be used to planarize the metallized structures 144, 146, 148, 156, interconnect structures 150, 152, first bottom contacts 128, and / or second bottom contacts 130.

[0062] As described above, Figures 2A to 2T are provided as examples only. Other examples may differ from those described with respect to Figures 2A to 2T.

[0063] Figures 3A to 3E are illustrations of an example embodiment 300 of the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing tools may be used to perform one or more semiconductor processing operations associated with Figures 3A to 3E, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0064] Turning to FIG. 3A, as an alternative to Example Embodiment 200 described in relation to FIGS. 2A to 2T, the trench capacitor structure 126a in Example Embodiment 300 is formed in a continuous interlayer dielectric layer 114b, instead of the alternating arrangement of interlayer dielectric layers 114b, 114c, 114d and etch stop layers 116b, 116c as shown in FIGS. 2A to 2T. In other respects, as shown in FIG. 3A, the process of forming the trench capacitor structure 126a on the first bottom contact 128 and the second bottom contact 130 is the same or substantially the same as that shown in FIGS. 2A to 2R.

[0065] As shown in FIG3A, an additional portion of the interlayer dielectric layer 114b is deposited using one or more deposition tools to increase the vertical height of the interlayer dielectric layer 114b in the z-direction, and an etch stop layer 116b and an interlayer dielectric layer 114c are deposited. In this manner, the interlayer dielectric layer 114 and the etch stop layer 116 can be aligned along the z-direction in the semiconductor device 100. Each interlayer dielectric layer 114 and each etch stop layer 116 can be deposited using one or more deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, the interlayer dielectric layer 114 and / or the etch stop layer 116 can be planarized using a planarization tool after deposition.

[0066] As further shown in FIG3A, a photoresist layer 302 is deposited on the top surface of the interlayer dielectric layer 114c. In some embodiments, a deposition tool can be used to form the photoresist layer 302 on the top surface of the interlayer dielectric layer 114c. An exposure tool can be used to expose the photoresist layer 302 to a radiation source to pattern the photoresist layer 302. A development tool can be used to develop and remove portions of the photoresist layer 302 to expose the pattern 304 shown in FIG3A. The pattern 304 in the photoresist layer 302 is used to etch the exposed portions of the interlayer dielectric layer 114c and the bottom portions of the interlayer dielectric layer 114b and the etch stop layers 116a, 116b to form an opening 306, exposing the top surface of the metallized structure 144 in the peripheral region 154. An etching tool can be used to etch the exposed portions of the interlayer dielectric layer 114c and the bottom portions of the interlayer dielectric layer 114b and the etch stop layers 116a, 116b according to the pattern to form the opening 306. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a hard mask layer is used as an alternative technique to etch the exposed portion of the interlayer dielectric layer 114c and the bottom portion of the interlayer dielectric layer 114b and the etch stop layers 116a, 116b according to a pattern to form the opening 306.

[0067] As shown in FIG. 3B, a light-blocking layer 308 is deposited in a portion of the opening 306, with a height lower than the etch stop layer 116b in the z-direction. In some embodiments, a deposition tool can be used to form the light-blocking layer 308 in the opening 306. An exposure tool can be used to further expose the photoresist layer 302 to the radiation source to widen the pattern 304 in the x-direction, forming a wider pattern 310 in the photoresist layer 302. A development tool can be used to develop and remove the extra portion of the photoresist layer 302 to expose the wider pattern 310 as shown in FIG. 3B. The wider pattern 310 in the photoresist layer 302 is used to etch the exposed portion of the interlayer dielectric layer 114c and the bottom portion of the interlayer dielectric layer 114b and the etch stop layer 116b to widen the upper portion of the opening 306 up to the top surface of the light-blocking layer 308. The upper portion of the opening 306 can be widened by etching the exposed portion of the interlayer dielectric layer 114c and the bottom portions of the interlayer dielectric layer 114b and the etch stop layer 116b according to a wider pattern 310 using an etching tool. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a hard mask layer is used as an alternative technique to pattern-etch the exposed portion of the interlayer dielectric layer 114c and the bottom portions of the interlayer dielectric layer 114b and the etch stop layer 116b to widen the upper portion of the opening 306. In some embodiments, the remaining portions of the photoresist layer 302 and the photoblocking layer 308 can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0068] As shown in FIG3C, after removing the remaining portions of the photoresist layer 302 and the photoblocking layer 308, one or more deposition tools can be used to deposit a deep interconnect structure (e.g., a deep via) 158 on the metallized structure 144 in the opening 306, and to deposit a metallized structure 160 on the upper deep interconnect structure 158 widened in the opening 306. As seen in FIG3C, a portion of the deposited metallized structure 160 is formed on the top surface of the interlayer dielectric layer 114c. The deep interconnect structure 158 and the metallized structure 160 are deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. As shown in FIG3D, which is a cross-sectional view of line GG in the top view of FIG3E, after depositing the metallized structure 160, a planarization tool can be used to planarize the metallized structure 160 to remove excess portions of the metallized structure 160 on the top surface of the interlayer dielectric layer 114c. In Example 300, the deep interconnect structure 158 formed by the continuous interlayer dielectric layer 114b simplifies the formation of interconnect and metallization structures in the peripheral region 154 compared to Example 200. For example, the deep interconnect structure 158 of Example 300 replaces the metallization structure 146 and interconnect structures 150, 152 of Example 200, which simplifies the manufacturing process by using less masking.

[0069] As shown in FIG3E, a plurality of metallization structures 160 (and underlying deep interconnect structures 158) may be formed in the peripheral region 154 of the semiconductor device 100. In addition, the semiconductor device 100 may include an array of trench capacitor structures 126a comprising a plurality of trench structures 218, 220, 222.

[0070] The trench capacitor structure 126a of example embodiments 200 and 300 uses a second bottom contact 130 to connect the top electrode layer 140 (e.g., CTM layer) to a voltage source (e.g., reset voltage), instead of forming a top via and contact above the metal-insulator-metal capacitor structure. Therefore, the capacitor area can be increased compared to a metal-insulator-metal capacitor structure using a top via connected to the CTM layer. Eliminating the top via connection also prevents plasma charge damage to the CTM layer that could occur during the etching process that forms the via landing on the CTM layer. Connecting the top electrode layer 140 to the second bottom contact 130 also facilitates local reset of the capacitor structure, as the bottom connection can be part of an existing metallization loop or an additional metallization layer to connect the capacitor structure to the reset voltage within the pixel, allowing the capacitor to be locally reset with a reduced resistance-capacitance time constant, resulting in faster capacitor reset speeds and increased frame rates compared to other capacitor structures.

[0071] As described above, Figures 3A to 3E are provided as examples. Other examples may differ from those described with respect to Figures 3A to 3E.

[0072] Figures 4A to 4N are diagrams of an example embodiment 400 forming the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing tools may be used to perform one or more semiconductor processing operations associated with Figures 4A to 4N, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0073] Turning to FIG4A, as an alternative to Example Embodiment 200 described in relation to FIGS. 2A to 2T and Example Embodiment 300 described in relation to FIGS. 3A to 3E, the trench capacitor structure 126b in Example Embodiment 400 includes a top electrode layer 162 arranged differently from the top electrode layer 140 of the trench capacitor structure 126a, and an additional layer deposited on the top electrode layer 162. In other respects, the process of forming the trench capacitor structure 126b on the first bottom contact 128 and the second bottom contact 130 as shown in FIG4A is the same or substantially the same as that shown in FIGS. 2A to 2N.

[0074] As shown in FIG4A, a top electrode layer 162 may be deposited on the exposed surface of the conductive layer 138 in trenches 202, 206, and 208, and on the exposed top surface of the second bottom contact 130 in trench 208. A portion of the top electrode layer 162 is formed above the second bottom contact 130 and may be in physical contact with the second bottom contact 130. In trenches 202, 206, and 208, the top electrode layer 162 is a conformal layer conforming to the sidewalls and bottom surfaces of trenches 202, 206, and 208. The top electrode layer 162 may also be deposited on the top surface of the conductive layer 138 on the interlayer dielectric layer 114d, and on the top surface of the conductive layer 138 between and / or adjacent to adjacent trenches 202, 206, and 208. In some embodiments, the top electrode layer 162 is conformally deposited using a deposition tool so that the top electrode layer 162 conforms to the contours of trenches 202, 206, and 208. In some embodiments, conformal chemical vapor deposition and / or atomic layer deposition techniques are used to deposit the top electrode layer 162.

[0075] In some embodiments, a barrier layer may be deposited on the exposed surfaces of the conductive layer 138 in trenches 202, 206, and 208, and on the exposed top surface of the second bottom contact 130 in trench 208, prior to the deposition of the top electrode layer 162. In this case, the barrier layer may be in physical contact with the top surface of the second bottom contact 130. In some embodiments, the barrier layer is conformally deposited using a deposition tool to conform to the contours of trenches 202, 206, and 208. In some embodiments, the barrier layer is deposited using conformal chemical vapor deposition and / or atomic layer deposition techniques. The barrier layer prevents conductive material (e.g., copper (Cu)) of the second bottom contact 130 from migrating upwards into the top electrode layer 162 and may include tantalum (Ta), tantalum nitride (TaN), and / or other suitable barrier materials. Regardless of the presence or absence of the barrier layer, the top electrode layer 162 is electrically connected to the second bottom contact 130.

[0076] As shown in FIG4B, a second insulating layer 164 may be deposited on the exposed surface of the top electrode layer 162 in trenches 202, 206, and 208. The second insulating layer 164 may also be deposited on the top surface of the top electrode layer 162 on the interlayer dielectric layer 114d, and on the top surface of the top electrode layer 162 between and / or adjacent to adjacent trenches 202, 206, and 208, so that the second insulating layer 164 can physically contact the top surface of the top electrode layer 162. In some embodiments, the second insulating layer 164 is conformally deposited using a deposition tool to conform to the contours of trenches 202, 206, and 208. In some embodiments, conformal chemical vapor deposition and / or atomic layer deposition techniques are used to deposit the insulating layer 136.

[0077] Similar to insulating layer 136, second insulating layer 164 may include one or more electrically insulating materials. In some embodiments, second insulating layer 164 includes one or more low-k dielectric materials, such as silicon oxide (SiOx, e.g., SiO2). Furthermore and / or alternatively, second insulating layer 164 may include one or more high-k dielectric materials, such as zirconium oxide (ZrOx, e.g., ZrO2), aluminum oxide (AlxOy, e.g., Al2O3), silicon nitride (SixNy, e.g., Si3N4), yttrium oxide (YxOy, e.g., Y2O3), lanthanum oxide (LaxOy, e.g., La2O3), and / or hafnium oxide (HfOx, e.g., HfO2). In some embodiments, second insulating layer 164 is a multilayer stack comprising multiple dielectric layers. For example, insulating layer 136 may include a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0078] As shown in FIG4C, an additional conductive layer 166 may be deposited on the exposed surface of the second insulating layer 164 in trenches 202, 206, and 208. Due to the deposition of the additional conductive layer 166, trench structures 402, 404, and 406 corresponding to trenches 202, 206, and 208 are formed, respectively. Each of the trench structures 402, 404, and 406 includes a plurality of conformal layers conforming to the contours of trenches 202, 206, and 208. In trench structure 402, the conformal layer may include a bottom electrode layer 134, an insulating layer 136 on the bottom electrode layer 134, a conductive layer 138 on the insulating layer 136, a top electrode layer 162 on the conductive layer 138, and a second insulating layer 164 on the top electrode layer 162. In trench structures 404 and 406, the conformal layer may include an insulating layer 136, a conductive layer 138 on the insulating layer 136, a top electrode layer 162 on the conductive layer 138 (except for the portion of the top electrode layer 162 formed on the top surface of the second bottom contact 130 in trench structure 406), and a second insulating layer 164 on the top electrode layer 162. Trench structures 404 and 406 do not include a bottom electrode layer 134. The bottom electrode layer 134, insulating layer 136, conductive layer 138, top electrode layer 162, and second insulating layer 164 may each conform to the contour of trench 202 such that the bottom electrode layer 134, insulating layer 136, conductive layer 138, top electrode layer 162, and second insulating layer 164 conform (e.g., along) the sidewalls and bottom surface of trench 202. Except for the exposed top surface of the second bottom contact 130 in trench 208, insulating layer 136 and conductive layer 138 may each conform to the contours of trenches 206 and 208, such that insulating layer 136 and conductive layer 138 conform (e.g., along) the sidewalls and bottom surfaces of trenches 206, 208. Top electrode layer 162 and second insulating layer 164 also each conform to the contours of trenches 206, 208, such that top electrode layer 162 and second insulating layer 164 conform (e.g., along) the sidewalls and bottom surfaces of trenches 206, 208. Trench capacitor structure 126b also includes an additional conductive layer 166 on the second insulating layer 164. In some embodiments, the additional conductive layer 166 is a filler layer filling the remaining areas of trenches 202, 206. The additional conductive layer 166 may include titanium nitride (TiN) and / or other suitable conductive materials.

[0079] As shown in FIG4D, in trench 208, the additional conductive layer 166 is a conformal layer conforming to the sidewalls and bottom surface of trench 208, and a dielectric plug layer 168 is also included in the remaining region of trench 208. The dielectric plug layer 168 may be, for example, an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric plug layer 168 may be deposited on the additional conductive layer 166 using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation (such as a CMP operation) may be performed using a planarization tool to planarize the dielectric plug layer 168 after deposition. Alternatively, a full-surface etching operation may be performed to reduce the thickness of the dielectric plug layer 168 in the z-direction.

[0080] The bottom electrode layer 134, insulating layer 136, and top electrode layer 162 correspond to the first metal-insulator-metal structure of the trench capacitor structure 126b. Therefore, the trench capacitor structure 126b can also be referred to as a metal-insulator-metal capacitor structure. The bottom electrode layer 134 (also called CBM) and the top electrode layer 162 (also called CTM) may each include one or more conductive metals, one or more conductive metallic materials, one or more conductive ceramic materials, and / or other types of conductive materials. For example, they include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 134 and the top electrode layer 162 include the same material or the same material composition. In some embodiments, the bottom electrode layer 134 and the top electrode layer 162 include different materials or different material compositions.

[0081] In addition to the first metal-insulator-metal structure, the trench capacitor structure 126b also includes a second insulating layer 164 and an additional conductive layer 166 located on the second insulating layer 164. The combination of the top electrode layer 162, the second insulating layer 164, and the additional conductive layer 166 corresponds to the second metal-insulator-metal structure of the trench capacitor structure 126b. Compared to the trench capacitor structure 126a in example embodiments 200 and 300, the addition of the second insulating layer 164 and the additional conductive layer 166 to the trench capacitor structure 126b in example embodiment 400 can increase the capacitance by approximately 2 times.

[0082] As shown in FIG4E, a first upper dielectric layer 170 is deposited on the dielectric plug layer 168, and a second upper dielectric layer 172 is deposited on the first upper dielectric layer 170. The first upper dielectric layer 170 may be, for example, a nitride (silicon oxynitride (SiON) and / or other nitride materials) and / or other types of dielectric materials. The second upper dielectric layer 172 may be, for example, a nitride (silicon nitride (SixNy) and / or other nitride materials) and / or other types of dielectric materials. The first upper dielectric layer 170 may be deposited on the dielectric plug layer 168 and the second upper dielectric layer 172 may be deposited on the first upper dielectric layer 170 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques and / or other suitable deposition techniques. In some implementations, a planarization operation (such as a chemical mechanical planarization operation) may be performed using a planarization tool to planarize the first upper dielectric layer 170 after deposition and / or the second upper dielectric layer 172 after deposition.

[0083] As shown in FIG4F, side portions of the second upper dielectric layer 172, the first upper dielectric layer 170, the dielectric plug layer 168, and the additional conductive layer 166 are removed to form a patterned trench capacitor structure 126b, wherein a portion of the second insulating layer 164 is exposed. In some embodiments, a masking layer is formed on a portion of the second upper dielectric layer 172, and an etching operation is performed to etch the portions not covered by the masking layer. The etching operation may include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. Gas etchants, such as oxygen (O2), argon (Ar), and / or fluorine-containing gases, may be used. Fluorine-containing etchants may include fluorocarbon (CFx)-based gas etchants, such as carbon tetrafluoride (CF4) gas etchants.

[0084] As shown in Figure 4G, a third upper dielectric layer 174 is deposited on the second upper dielectric layer 172, surrounding the sides of the first upper dielectric layer 170 and the second upper dielectric layer 172, as well as the sides of the dielectric plug layer 168, and deposited on the exposed top surface of the second insulating layer 164. A fourth upper dielectric layer 176 is conformally deposited on the third upper dielectric layer 174. The third upper dielectric layer 174 may be, for example, an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials) and / or other types of dielectric materials. The fourth upper dielectric layer 176 may be, for example, a nitride (silicon nitride (SixNy) and / or other nitride materials) and / or other types of dielectric materials. The third upper dielectric layer 174 and the fourth upper dielectric layer 176 may be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques.

[0085] As shown in FIG4H, a blanket etching operation is performed to remove portions of the third upper dielectric layer 174 and the fourth upper dielectric layer 176, as well as portions of the second insulating layer 164, the top electrode layer 162, and the conductive layer 138, resulting in the exposure of portions of the insulating layer 136. In some embodiments, the blanket etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0086] As shown in FIG4I, a fifth upper dielectric layer 178 is deposited on the second upper dielectric layer 172, a portion of the third upper dielectric layer 174, surrounding the sides of the third upper dielectric layer 174 and the fourth upper dielectric layer 176, and deposited on the exposed top surface of the insulating layer 136. A sixth upper dielectric layer 180 is conformally deposited on the fifth upper dielectric layer 178. The fifth upper dielectric layer 178 may be, for example, an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials) and / or other types of dielectric materials. The sixth upper dielectric layer 180 may be, for example, a nitride (silicon nitride (SixNy) and / or other nitride materials) and / or other types of dielectric materials. The fifth upper dielectric layer 178 and the sixth upper dielectric layer 180 may be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques.

[0087] As shown in FIG4J, a blanket etching operation is performed to remove portions of the fifth upper dielectric layer 178 and the sixth upper dielectric layer 180, as well as portions of the bottom insulating layer 136, the bottom electrode layer 134, and the interlayer dielectric layer 114d. In some embodiments, the blanket etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0088] As shown in Figure 4K, an additional portion of the interlayer dielectric layer 114d is deposited using one or more deposition tools to increase the vertical height of the interlayer dielectric layer 114d in the z-direction. The additional portion of the interlayer dielectric layer 114d can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques using one or more deposition tools.

[0089] FIG4L illustrates a wider view of the semiconductor device 100 in the x-direction in Example Embodiment 400, showing a peripheral region 182 including interconnect structure 184 and metallization structure 186. FIG4L further illustrates that, in some embodiments, a planarization tool can be used to planarize an additional portion of the interlayer dielectric layer 114d after deposition. As shown in FIG4L, the metallization structure 186 and the interconnect structure (e.g., via) 184 are formed in the peripheral region 182, laterally adjacent to the trench capacitor structure 126b in the x-direction.

[0090] Various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form the metallization structure 186 and the interconnect structure 184. In some embodiments, the first bottom contact 128, the second bottom contact 130, the metallization structure 186, and the interconnect structure 184 may be formed in multiple layers. For example, an interlayer dielectric layer 114 and an etch stop layer 116 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), grooves may be formed in and / or through the interlayer dielectric layer 114 and the etch stop layer 116 (e.g., using exposure tools, developing tools, and / or etching tools), and a layer including the first bottom contact 128 and the second bottom contact 130 (e.g., an MO layer) may be formed in the interlayer dielectric layer 114a and the etch stop layer 116a (e.g., using one or more deposition tools and / or one or more planarization tools). Another interlayer dielectric layer 114b and another etch stop layer 116b may be formed, and a layer including the interconnect structure 184 (e.g., a V0 layer) may be formed in the interlayer dielectric layer 114b and the etch stop layer 116b. The remaining layers may be formed in a similar manner.

[0091] The metallized structure 186, interconnect structure 184, first bottom contact 128 and / or second bottom contact 130 can be deposited using one or more deposition tools employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, the metallized structure 186, interconnect structure 184, first bottom contact 128 and / or second bottom contact 130 can be planarized using a planarization tool after deposition.

[0092] As shown in FIG4M, an etch stop layer 116d and an interlayer dielectric layer 114e are deposited using one or more deposition tools. In this manner, the interlayer dielectric layer 114 and the etch stop layer 116 can be aligned along the z-direction in the semiconductor device 100. Each interlayer dielectric layer 114 and each etch stop layer 116 can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation, and / or other suitable deposition techniques using one or more deposition tools. In some embodiments, the interlayer dielectric layer 114 and / or the etch stop layer 116 can be planarized using a planarization tool after deposition.

[0093] As shown in FIG4N, a metallization structure 190 and interconnect structures (e.g., vias) 188 and 192 are formed. The interconnect structure 188 is formed in the peripheral region 182 in the x-direction, located on the side of the trench capacitor structure 126b; the metallization structure 190 is formed in the peripheral region 182 in the z-direction and located above the trench capacitor structure 126b. The interconnect structure 192 extends from the metallization structure 190, passes through the interlayer dielectric layer 114d, the second upper dielectric layer 172, the first upper dielectric layer 170, and the dielectric plug layer 168, and enters the additional conductive layer 166, so that the interconnect structure 192 is in physical contact with the additional conductive layer 166.

[0094] Various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form the metallized structure 190 and the interconnect structures 188, 192. The metallized structure 190 and the interconnect structures 188, 192 can be deposited using one or more deposition tools employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the metallized structure 190 and / or the interconnect structures 188, 192 can be planarized using a planarization tool after deposition.

[0095] As described above, Figures 4A to 4N are provided as examples. Other examples may differ from those described with respect to Figures 4A to 4N.

[0096] FIG5 is a circuit diagram 500 of an example embodiment 400 of the trench capacitor structure 126b described in relation to FIG4N. As shown in FIG5, the trench capacitor structure 126b includes a first metal-insulator-metal capacitor 502 and a second metal-insulator-metal capacitor 504. The bottom electrode layer 134, the insulating layer 136, and the top electrode layer 162 correspond to the first metal-insulator-metal capacitor 502, while the top electrode layer 162, the second insulating layer 164, and the additional conductive layer 166 correspond to the second metal-insulator-metal capacitor 504. Compared with the trench capacitor structure 126a, the addition of the second metal-insulator-metal capacitor 504 in the trench capacitor structure 126b of example embodiment 400 may increase the capacitance by approximately 2 times, according to the following equation: where CTotal refers to the total capacitance, C1 is the capacitance of the first metal-insulator-metal capacitor 502, and C2 is the capacitance of the second metal-insulator-metal capacitor 504. The first bottom contact 128 (capacitor network 2) is connected to the bottom electrode layer 134, which serves as the bottom electrode of the first metal-insulator-metal capacitor 502. The first bottom contact 128 (capacitor network 2) is also connected to the metallization structure 190 (capacitor network 3) via a combination of metallization structure 186 and interconnect structures 184, 188. The metallization structure 190 is connected to an additional conductive layer 166 via interconnect structure 192, which serves as the top electrode of the second metal-insulator-metal capacitor 504. The second bottom contact 130 (capacitor network 1) is connected to the top electrode layer 162, which serves as the top electrode of the first metal-insulator-metal capacitor 502 and the bottom electrode of the second metal-insulator-metal capacitor 504.

[0097] As described above, Figure 5 is provided as an example. Other examples may differ from those described with respect to Figure 5.

[0098] FIG6A is a diagram of an example semiconductor device 600 described herein. Semiconductor device 600 may include an example of a three-dimensional image sensor (e.g., a three-dimensional complementary metal-oxide-semiconductor image sensor). Semiconductor device 600 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light sensing embodiments.

[0099] As shown in FIG6A, the semiconductor device 600 may include a three-dimensional stacked structure, wherein semiconductor structures 600a and 600b are stacked and vertically arranged in the semiconductor device 600. Semiconductor structures 600a and 600b may each be semiconductor dies, semiconductor wafers, and / or other types of semiconductor structures formed on a wafer, diced into dies, and then bonded together.

[0100] Semiconductor structure 600a may be an image sensor die including pixel sensor array 602. Semiconductor structure 600a may also include black level correction (BLC) region 604, bonding pad region 606, and / or sealing ring region 608, etc. Pixel sensor array 602 may include a plurality of pixel sensors 610 arranged in an array. Pixel sensors 610 may be configured to sense incident light and convert photons of the incident light into photocurrent. Pixel sensors 610 may be contained in device layer 612 of semiconductor structure 600a. Each pixel sensor 610 may include one or more photodiodes 614 configured to generate photocurrent based on photons of incident light. The pixel sensor 610 may also include floating diffusion nodes 616 in the device layer 612, configured to temporarily store photocurrent generated by the associated pixel sensor 610, and may each include a transmission gate 618 configured to control the photocurrent flow from the photodiode 614 to the floating diffusion node 616. The pixel sensor 610 may be formed by one or more semiconductor processing tools using various semiconductor processing techniques, such as photolithography, etching, deposition, chemical mechanical planarization, and / or ion implantation.

[0101] The black level correction (BLC) region 604 includes a metal shielding layer located above a portion of the device layer 612 to allow baseline current measurements to be performed in the device layer 612 of the black level correction (BLC) region 604 to determine the dark current of the pixel sensor array 602 (e.g., current generated in the device layer 612 by a non-incident light source such as heat), thereby adjusting the black level of the pixel sensor array 602 to compensate for the dark current. The bonding pad region 606 may include one or more conductive bonding pads (or electronic pads) and / or metallization layers, through which electrical connections between the semiconductor structure 600a and external devices and / or external packages can be established. The sealing ring region 608 may include an arrangement of metallization structures and interconnect structures to provide structural rigidity to the semiconductor structure 600a and protect the semiconductor structure 600a from moisture and other contaminants.

[0102] As further shown in FIG6A, the semiconductor structure 600a may include an interconnect layer 620 located below the device layer 612. The interconnect layer 620 may include a dielectric region 622, which includes one or more dielectric layers (e.g., interlayer dielectric layer, interlayer metal dielectric layer, etch stop layer) and an arrangement of metallization structures 624 and interconnect structures 626 in the dielectric region 622.

[0103] As further shown in FIG6A, one or more overflow capacitors 628 may be included in interconnect layer 620. The overflow capacitor 628 may be structurally implemented as trench capacitor structure 126a or trench capacitor structure 126b shown and described herein. The overflow capacitor 628 may be electrically coupled to floating diffusion node 616 of pixel sensor 610 and may be configured to store overflow photocurrent from floating diffusion node 616.

[0104] Semiconductor structure 600b may be a processor die, a dedicated integrated circuit die, and / or other types of semiconductor dies including integrated circuit devices 630 in device layer 632. Integrated circuit devices 630 may include transistors, capacitors, and / or other types of integrated circuit devices configured to process signals generated by semiconductor die 600a.

[0105] As further shown in FIG6A, the semiconductor structure 600b may include an interconnect layer 634 located above the device layer 632. The interconnect layer 634 may include a dielectric region 636, which includes one or more dielectric layers (e.g., interlayer dielectric layer, interlayer metal dielectric layer, etch stop layer) and an arrangement of metallization structures 638 and interconnect structures 640 in the dielectric region 636.

[0106] As further shown in FIG6A, semiconductor structures 600a and 600b may be bonded together at a bonding interface 642 between interconnect layers 620 and 634. A bonding structure 644 (e.g., bonding pad, bonding via) on semiconductor structure 600a may be bonded to a bonding structure 644 (e.g., bonding pad, bonding via) on semiconductor structure 600b at the bonding interface 642 in a metal-to-metal bonding manner. Furthermore and / or alternatively, dielectric regions 622 of semiconductor structure 600a and dielectric regions 636 of semiconductor structure 600b may be bonded together at the bonding interface 642 in a dielectric-to-dielectric bonding manner.

[0107] FIG6B is an example circuit diagram of the pixel sensor 610 described herein. The pixel sensor 610 may include a front pixel sensor (e.g., a pixel sensor configured to receive photons from the front of the sensor die), a back pixel sensor (e.g., a pixel sensor configured to receive photons from the back of the sensor die), and / or other types of pixel sensors.

[0108] As shown in the example circuit of Figure 6B, the pixel sensor 610 includes a photodiode 614 configured to sense and / or accumulate incident light (e.g., light directed toward the pixel sensor 610) and convert photons of the incident light into a photocurrent. The magnitude of the photocurrent may be based on the number of photons collected in the photodiode 614 (e.g., the intensity of the incident light). Therefore, the accumulation of photons in the photodiode 614 produces an accumulation of charge, which represents the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a smaller amount of charge may correspond to a lower intensity or brightness).

[0109] The photodiode 614 is electrically connected to the transmission gate 618. The transmission gate 618 is configured to control the transmission of photocurrent from the photodiode to the floating diffusion node 616. The transmission gate 618 can be selectively switched by applying a transmission voltage (Vtx) to the transmission gate 618. In some embodiments, the transmission voltage applied to the transmission gate 618 causes a leakage path (e.g., an embedded channel) to be formed across the transmission gate 618 between the photodiode 614 and the floating diffusion node 616, allowing the photocurrent to be transmitted along the leakage path to the floating diffusion node 616. In some embodiments, removing the transmission voltage from the transmission gate 618 (or the absence of the transmission voltage) causes the leakage path to be removed, preventing the photocurrent from being transmitted from the photodiode 614 to the floating diffusion node 616.

[0110] The circuitry of the pixel sensor 610 may further include a reset gate 634. The reset gate 634 is electrically connected to a voltage source 636. The reset gate 634 may be controlled to selectively apply a reset voltage (Vrst) from the voltage source 636 to the floating diffusion node 616. The transmission gate 618 and the reset gate 634 may be electrically coupled to the floating diffusion node 616 such that the reset voltage is applied to the floating diffusion node 616 to "reset" the floating diffusion node 616 (e.g., by draining any residual charge in the floating diffusion node 616), which occurs before activating the transmission gate 618 to transfer photocurrent from the photodiode 614 to the floating diffusion node 616.

[0111] The pixel sensor 610 can be a lateral overflow integration capacitor (LOFIC) pixel sensor, which includes an overflow gate 632 and an overflow capacitor 630. The overflow capacitor 630 can be electrically coupled to the floating diffusion node 616 through the overflow gate 632, so that photocurrent can be transferred from the floating diffusion node 616 to the overflow capacitor 630 for temporary storage. The overflow gate 632 can selectively control the flow of photocurrent to and / or from the overflow capacitor 630. This allows additional photocurrent to be transferred from the photodiode 614 to the floating diffusion node 616 without causing the pixel sensor 610 to saturate, thereby increasing the full-well capacity and dynamic range of the pixel sensor 610.

[0112] The photocurrent can be used to apply a floating diffusion voltage (Vfd) to the source follower gate 638 of the pixel sensor 610 circuit. This allows the photocurrent to be observed without removing or discharging the photocurrent from the floating diffusion node 616 and / or the overflow capacitor 630. A reset gate 634 can be used instead to remove or discharge the photocurrent from the floating diffusion node 616 and / or the overflow capacitor 630. The capacitor top metal (CTM) layer of the overflow capacitor 630 is coupled to the drain side and drain voltage (Vdd) of the reset gate 634 via a second bottom contact 130. The CTM layer of the overflow capacitor 630 is coupled to the source side of the reset gate 634 via a first bottom contact 128.

[0113] To apply the floating diffusion voltage to the source follower gate 638, the transfer gate 618 can be turned off (e.g., to prevent the photocurrent from flowing back to the photodiode 614) and the overflow gate 632 can be turned on. This configuration allows the photocurrent stored in the floating diffusion node 616 and the overflow capacitor 630 to be used to apply the floating diffusion voltage to the source follower gate 638.

[0114] The source follower gate 638 serves as a high-impedance amplifier for the pixel sensor 610. The source follower gate 638 provides voltage-to-current conversion for the floating diffuse voltage. The output of the source follower gate 638 is electrically connected to a horizontal selection gate 640, which is configured to control the flow of photocurrent to external circuitry. The horizontal selection gate 640 is controlled by selectively applying a selection voltage (Vdi) to its gate. This allows photocurrent to flow to the output of the pixel sensor 610.

[0115] As described above, Figures 6A and 6B provide examples. Other examples may differ from those shown in Figures 6A and 6B.

[0116] FIG7 is a flowchart of an example process 700 associated with forming a semiconductor device. In some embodiments, one or more process blocks of FIG7 are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools.

[0117] As shown in FIG7, process 700 may include forming a first contact (block 710) in a dielectric layer. For example, one or more semiconductor processing tools may be used to form the first contact (e.g., first bottom contact 128) in a dielectric layer (e.g., interlayer dielectric layer 114a), as described herein.

[0118] As further shown in FIG. 7, process 700 may include forming a second contact (block 720) in a dielectric layer. For example, the second contact (e.g., second bottom contact 130) may be formed in the dielectric layer using one or more semiconductor processing tools, as described herein. In some embodiments, the second contact is adjacent to and spaced apart from the first contact. In some embodiments, the first and second contacts (e.g., first bottom contact 128 and second bottom contact 130) are formed by the same deposition process. For example, operations of blocks 710 and 720 may be performed simultaneously or as part of the same step. In some embodiments, the first and second contacts (e.g., first bottom contact 128 and second bottom contact 130) are formed by separate deposition processes. For example, operations of blocks 710 and 720 may be performed sequentially as part of different steps.

[0119] As further shown in FIG7, process 700 may include forming a first trench (block 730) over the first contact. For example, one or more semiconductor processing tools may be used to form the first trench (e.g., trench 202) over the first contact, as described herein. In some embodiments, the top surface of the first contact is exposed at the bottom of the first trench.

[0120] As further shown in FIG7, process 700 may include forming a first electrode layer (block 740) of a capacitor structure on the top surface of the first contact in the first trench. For example, one or more semiconductor processing tools may be used to form a first electrode layer (e.g., bottom electrode layer 134) of a capacitor structure (e.g., trench capacitor structure 126a or trench capacitor structure 126b) on the top surface of the first contact in the first trench, as described herein.

[0121] As further shown in FIG7, process 700 may include forming a second trench (block 750) over the second contact. For example, one or more semiconductor processing tools may be used to form the second trench (e.g., trench 208) over the second contact, as described herein.

[0122] As further shown in FIG7, process 700 may include an insulating layer (block 760) forming a capacitor structure in a first trench and a second trench. For example, one or more semiconductor processing tools may be used to form the insulating layer (e.g., insulating layer 136) of the capacitor structure in the first trench and the second trench, as described herein. In some embodiments, the insulating layer is on a first electrode layer in the first trench and on the bottom surface of the second trench.

[0123] As further shown in FIG7, process 700 may include removing a portion of the insulating layer and a portion of the bottom surface of the second trench to expose the top surface of the second contact (block 770). For example, one or more semiconductor processing tools may be used to remove a portion of the insulating layer and a portion of the bottom surface of the second trench to expose the top surface of the second contact, as described herein.

[0124] As further shown in FIG7, process 700 may include forming a second electrode layer (block 780) of a capacitor structure on an insulating layer in a first trench and a second trench. For example, one or more semiconductor processing tools may be used to form the second electrode layer of the capacitor structure (e.g., top electrode layer 140 or top electrode layer 162) on an insulating layer in a first trench and a second trench, as described herein. In some embodiments, a portion of the second electrode layer is formed on the top surface of the second contact.

[0125] Process 700 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with one or more other processes described elsewhere herein.

[0126] In a first embodiment, process 700 includes forming an additional insulating layer (e.g., a second insulating layer 164) on a second electrode layer in a first trench and a second trench, wherein the first electrode layer is formed along the sidewall and bottom surface of the first trench, and wherein the insulating layer, the second electrode layer and the additional insulating layer are formed along the sidewall and bottom surface of the first trench and along the sidewall and bottom surface of the second trench.

[0127] In the second embodiment, alone or in combination with the first embodiment, process 700 includes forming a conductive layer (e.g., an additional conductive layer 166) on an additional insulating layer (e.g., a second insulating layer 164) in the first trench and the second trench, and forming a third contact (e.g., a metallized structure 190) on the capacitor structure, wherein a via (e.g., an interconnect structure 192) is formed between the third contact and the conductive layer to electrically connect the third contact to the conductive layer.

[0128] In the third embodiment, the third contact is electrically connected to the first contact, either alone or in combination with one or more of the first and second embodiments.

[0129] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the third contact is electrically connected to the first contact through at least one via (e.g., interconnect structure 184 and / or interconnect structure 188) formed between the third contact and the first contact and on one side of the capacitor structure.

[0130] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, a conductive layer (e.g., protective conductive layer 132) is formed along the opposite sidewalls of the first trench on opposite sides of the first electrode layer.

[0131] Although Figure 7 shows several exemplary blocks of process 700, in some embodiments, process 700 includes more blocks, fewer blocks, different blocks, or blocks arranged differently compared to those shown in Figure 7. Additionally or alternatively, two or more blocks of process 700 may be executed in parallel.

[0132] Thus, the top electrode layer of the pixel sensor's capacitor structure is connected to a bottom contact (e.g., opposite to the top connection) of the semiconductor device interconnect layer, which is located at the bottom of the capacitor structure, and connects the top electrode layer to the pixel sensor's reset voltage source and reset transistor, without the need for additional vias, metallization layers, and / or other conductive interconnect structures extending along the capacitor structure. Therefore, the lateral footprint of the capacitor structure can be increased, thereby increasing the capacitor area of ​​the capacitor structure.

[0133] Using a bottom contact also prevents the top electrode layer from being damaged by plasma charge, because the top electrode layer is formed on the bottom contact, rather than forming a top connection on the top electrode layer. Therefore, plasma charge damage that could occur when forming a groove for the top connection during the etching process is avoided. Connecting the top electrode layer to the bottom contact also helps to enable local reset functionality for pixel sensors and other pixel sensors in a pixel sensor array within a semiconductor device. For example, the bottom connection may be part of an existing metallization circuit or an additional metallization layer for connecting the capacitive structure of the pixel sensor to a reset voltage source, allowing the capacitive structure to be locally reset with a reduced RC time constant, resulting in faster capacitive reset speeds and higher frame rates compared to other pixel sensor arrays. In some embodiments, in addition to providing a bottom contact structure, capacitance is further increased by using a trench capacitor structure with a second metal-insulator-metal structure on a first metal-insulator-metal structure.

[0134] As described above, some embodiments described herein provide a semiconductor device. The semiconductor device includes one or more dielectric layers. The semiconductor device includes a capacitor structure disposed within the one or more dielectric layers. The capacitor structure includes one or more trench structures. The capacitor structure includes a first electrode layer in the one or more trench structures, an insulating layer on the first electrode layer in the one or more trench structures, and a second electrode layer on the insulating layer in the one or more trench structures. The semiconductor device includes a first bottom contact under the one or more trench structures along a first direction. The first electrode layer is electrically connected to the first bottom contact. The semiconductor device includes a second bottom contact laterally adjacent to one side of the first bottom contact in a second direction substantially perpendicular to the first direction, wherein the second electrode layer is electrically connected to the second bottom contact, and at least a portion of the second electrode layer is located above the second bottom contact.

[0135] As described above, some embodiments described herein provide a method. The method includes forming a first bottom contact in a dielectric layer. The method includes forming a second bottom contact in a dielectric layer, wherein the second bottom contact is adjacent to and spaced apart from the first bottom contact. The method includes forming a first trench over the first bottom contact, wherein the top surface of the first bottom contact is exposed at the bottom of the first trench. The method includes forming a first electrode layer of a capacitor structure on the top surface of the first bottom contact in the first trench. The method includes forming a second trench over a second bottom contact. The method includes forming an insulating layer of a capacitor structure in the first trench and the second trench, wherein the insulating layer is located on the first electrode layer in the first trench and on the bottom surface of the second trench. The method includes removing portions of the insulating layer and portions of the bottom surface of the second trench to expose the top surface of the second bottom contact. The method includes forming a second electrode layer of a capacitor structure on the insulating layer in the first trench and the second trench, wherein portions of the second electrode layer are formed on the top surface of the second bottom contact.

[0136] As described above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a capacitor structure. The capacitor structure includes a first conductive layer on the sidewalls and bottom surface of a trench structure, a second conductive layer in the trench structure, and an insulating layer between the first and second conductive layers. The semiconductor device includes a first bottom contact below the bottom surface of the trench structure, wherein the first conductive layer is located on the first bottom contact. The semiconductor device includes a second bottom contact laterally adjacent to the first bottom contact, wherein the second conductive layer is located on the second bottom contact.

[0137] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within a range of 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not restrictive. It should be understood that the terms "approximately" and "substantially" can refer to a percentage of the value of the quantity given according to this disclosure.

[0138] The foregoing has summarized features of various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0139] The following detailed description, taken in conjunction with the accompanying drawings, will provide the best understanding of the nature of this disclosure. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A and 1B are illustrations of example semiconductor devices described herein. Figures 2A to 2T are illustrations of example embodiments forming the semiconductor devices described herein. Figures 3A to 3E are illustrations of example embodiments forming the semiconductor devices described herein. Figures 4A to 4N are illustrations of example embodiments forming the semiconductor devices described herein. Figure 5 is a circuit diagram of an example embodiment of the capacitor structure described herein. Figure 6A is an illustration of an example semiconductor device described herein. Figure 6B is an example circuit diagram of a pixel sensor described herein. Figure 7 is a flowchart of an example process related to forming the semiconductor devices described herein.

Claims

1. A semiconductor device, comprising: One or more dielectric layers; A capacitor structure located within one or more dielectric layers, wherein the capacitor structure comprises: one or more trench structures; a first electrode layer located within the one or more trench structures; an insulating layer located on the first electrode layer within the one or more trench structures; and a second electrode layer located on the insulating layer within the one or more trench structures; a first bottom contact located below the one or more trench structures along a first direction, wherein the first electrode layer is electrically connected to the first bottom contact; and a second bottom contact located laterally adjacent to the first bottom contact in a second direction perpendicular to the first direction, wherein the second electrode layer is electrically connected to the second bottom contact, and wherein at least a portion of the second electrode layer is located on the top surface of the second bottom contact, and the top surface of the first bottom contact is coplanar with the top surface of the second bottom contact.

2. The semiconductor device of claim 1, wherein the capacitor structure further includes one or more additional trench structures laterally adjacent to the one or more trench structures in the second direction; and wherein the one or more additional trench structures include the insulating layer and a second electrode layer located on the insulating layer in the one or more additional trench structures.

3. The semiconductor device of claim 1, wherein the capacitor structure further includes a conductive layer located between the insulating layer and the second electrode layer in the one or more trench structures.

4. The semiconductor device of claim 1, wherein the capacitor structure further includes a conductive layer laterally adjacent to the one or more trench structures in the second direction; and wherein the conductive layer is located on one side of the first electrode layer.

5. The semiconductor device of claim 1, wherein the capacitor structure further includes an additional insulating layer on the first electrode layer located in the one or more trench structures.

6. A method for forming a semiconductor device, comprising: The first bottom contact is formed in the dielectric layer; A second bottom contact is formed in the dielectric layer, wherein the second bottom contact is adjacent to and spaced apart from the first bottom contact; A first trench is formed above the first bottom contact, wherein the top surface of the first bottom contact is exposed at the bottom of the first trench; a first electrode layer of a capacitor structure is formed on the top surface of the first bottom contact in the first trench; a second trench is formed above the second bottom contact; an insulating layer of the capacitor structure is formed in the first trench and the second trench, wherein the insulating layer is located on the first electrode layer in the first trench and on the bottom surface of the second trench; a portion of the insulating layer and a portion of the bottom surface of the second trench are removed to expose the top surface of the second bottom contact, wherein the second bottom contact is laterally adjacent to the first bottom contact, and the top surface of the first bottom contact and the top surface of the second bottom contact are coplanar; and a second electrode layer of the capacitor structure is formed on the insulating layer in the first trench and the second trench, wherein a portion of the second electrode layer is formed on the top surface of the second bottom contact.

7. The method of forming a semiconductor device as described in claim 6 further includes: In the first trench and the second trench, an additional insulating layer is formed on the second electrode layer, wherein the first electrode layer is formed along the sidewall and bottom surface of the first trench; and wherein the insulating layer, the second electrode layer and the additional insulating layer are formed along the sidewall and bottom surface of the first trench, and along the sidewall and bottom surface of the second trench.

8. A method of forming a semiconductor device as claimed in claim 6, wherein a conductive layer is formed on opposite sides of the first electrode layer along opposite sidewalls of the first trench.

9. A semiconductor device, comprising: A capacitor structure includes: a first conductive layer located on the sidewalls and bottom surface of a trench structure; a second conductive layer located within the trench structure; an insulating layer located between the first conductive layer and the second conductive layer; a first bottom contact located below the bottom surface of the trench structure, wherein the first conductive layer is located on the top surface of the first bottom contact; and a second bottom contact laterally adjacent to the first bottom contact, wherein the second conductive layer is located on the top surface of the second bottom contact, and the top surface of the first bottom contact and the top surface of the second bottom contact are coplanar.

10. The semiconductor device of claim 9, wherein the second conductive layer is located on the second bottom contact at the bottom of the additional trench structure; and wherein the additional trench structure is laterally adjacent to the trench structure.