Semiconductor device and methods of formation

TW202630938APending Publication Date: 2026-07-16TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
TW114121006
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-04-10
Filing Date
2025-06-05
Publication Date
2026-07-16
Patent Text Reader

Abstract

Sacrificial test pads are formed in a semiconductor device and used for testing operations prior to bonding the semiconductor device with another semiconductor device to form a stacked semiconductor device. The sacrificial test pads may be formed in the interconnect layer, and may be formed of materials that enable the sacrificial test pads to be integrated into the manufacturing processes for the metallization of the interconnect layer. To prevent or reduce the likelihood of the uneven topographies of the sacrificial test pads from degrading bonding performance of the semiconductor devices, a planarization operation may be performed to planarize the surfaces of the sacrificial test pads. The sacrificial test pads may be subsequently covered by a dielectric layer to reduce the likelihood of oxidation of the sacrificial test pads. Retaining the sacrificial test pads, in turn, reduces the likelihood of oxidation of metallization structures under the sacrificial test pads.
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