Vertically stacked 8t complementary fet SRAM

Abstract

A static random access memory (SRAM) integrated circuit comprises a plurality of PMOS and NMOS transistors connected to a first storage node and a second storage node. The PMOS transistors are fabricated in an upper layer of the integrated circuit and the NMOS transistors are fabricated in a lower layer of the integrated circuit. A voltage supply rail, a write word line, a read bit line and a read word line are formed in the upper layer. A ground rail, a write bit line and a complementary write bit line are formed in the lower layer.

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