Semiconductor device and method of forming the same

A high-voltage FinFET device with a control and secondary gate structure addresses electric field management and depletion challenges, optimizing substrate use and performance by using a highly doped channel and trapping layers to enhance on-current and reduce depletion.

TW202633124APending Publication Date: 2026-08-01TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
TW114116202
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-10-15
Filing Date
2025-04-29
Publication Date
2026-08-01

AI Technical Summary

Technical Problem

As semiconductor devices continue to increase integration density by reducing minimum feature sizes, challenges arise in managing electric fields and depletion regions within high-voltage applications, leading to increased substrate area requirements and reduced performance.

Method used

The implementation of a high-voltage FinFET device with a control gate and a secondary modulation or depletion gate structure, utilizing a highly doped channel and trapping layers to manage electric fields and reduce channel depletion, thereby optimizing substrate area and performance.

Benefits of technology

The solution effectively reduces electric field strength during off-states, minimizes channel depletion, and enhances on-current, allowing for more efficient use of substrate space and improved high-voltage performance in semiconductor devices.

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Abstract

A semiconductor structure is disclosed that includes: a source region and a drain region in a substrate; a first gate structure disposed above a first channel region in the substrate and between the source region and the drain region wherein the first gate structure includes a first gate dielectric disposed above the first channel region and a first gate electrode disposed above the first gate dielectric; and a second gate structure disposed above a second channel region in the substrate and between the first gate structure and the drain region, wherein the first gate structure is disposed closer to the source region and the second gate structure is disposed closer to the drain region.
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