Patterning semiconductor materials using surface modification techniques
The method addresses the challenge of precise etch selectivity and contour control in semiconductor manufacturing by using a plasma-treated surface modification layer to achieve varying etch rates, reducing complexity and mitigating etch hysteresis without additional layers, enabling efficient formation of features with different critical dimensions.
Patent Information
- Application Number
- TW114136320
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-09-26
- Filing Date
- 2025-09-22
- Publication Date
- 2026-08-01
AI Technical Summary
The challenge in semiconductor manufacturing lies in achieving precise etch selectivity and contour control as feature sizes shrink, leading to complex patterning schemes and etching defects, necessitating multiple processes and additional layers that complicate and prolong the manufacturing process.
A method involving a plasma treatment to form a surface modification layer with enhanced etch selectivity, allowing different regions of the semiconductor layer to be removed at varying rates, thereby forming features of varying depths without the need for additional etch stop layers, and enabling precise control over etch resistance and selectivity.
This method achieves precise etch selectivity and contour control, mitigating etch hysteresis and reducing process complexity by allowing features of different critical dimensions to be formed efficiently, without requiring additional thin films or etch formulation changes, and can be tailored to adjust etch resistance and selectivity.