Substrate arrangement, method for producing an electronic assembly, and electronic assembly

TW202634122APending Publication Date: 2026-08-16HERAEUS ELECTRONIC GMBH & CO KG
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Patent Information

Application Number
TW115103005
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-01-31
Filing Date
2026-01-26
Publication Date
2026-08-16

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Patent Text Reader

Abstract

The invention relates to a substrate arrangement, to a method for producing an electronic assembly, and to an electronic assembly. The substrate arrangement comprises: (a) a metal foil that comprises a metal foil upper side and a metal foil underside, wherein the metal foil comprises a copper layer that has a copper layer upper side and a copper layer underside, and wherein the metal foil upper side is formed by the copper layer upper side, and (b) a contacting layer that is arranged on the metal foil underside, characterized in that the copper layer of the metal foil meets the condition K1 / D =
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