Capacitor detection structure and capacitor detection method

Abstract

A capacitor detection structure includes a wafer with a cutting line and a structure for detection on the cutting line. The structure for detection includes a route, a plurality of capacitor lower electrodes, a high-k (high dielectric constant) dielectric layer, and a support structure. The route is disposed in the cutting line of the wafer. The capacitor lower electrodes are disposed on the cutting line, and in the capacitor lower electrodes, a first part is connected to the route, and a second part is not connected to the route. The high-k dielectric layer is located on the outer sidewall and inner sidewall of the capacitor lower electrodes. The support structure connects sidewalls of the top of each of the capacitor lower electrodes and has a plurality of openings, and the top surface of the support structure has no a high-k dielectric layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor detection technology, and more particularly to a capacitor detection structure and a capacitor detection method. [Previous Technology]

[0002] To increase capacitance, capacitors in existing semiconductor devices mostly employ a high-density structure. Therefore, it is necessary to inspect each layer of the capacitor structure to ensure that no short circuit occurs between adjacent electrodes. Commonly used inspection tools include electron beam testing tools.

[0003] However, in electron beam detection of stress caused by high-k dielectric layers, it is difficult to determine the location and extent of short circuits due to high noise. [Summary of the Invention]

[0004] The present invention provides a capacitor detection structure that can accurately detect the location of defects.

[0005] The present invention also provides a capacitor detection method, which can improve the accuracy of identifying defect locations.

[0006] A capacitor detection structure according to the present invention includes a wafer with diced channels and a detection structure located on the diced channels of the wafer. The detection structure includes a circuit, a plurality of lower capacitor electrodes, a high dielectric constant dielectric layer, and a support structure. The circuit is disposed in the diced channels of the wafer. The lower capacitor electrodes are located on the diced channels, and a first portion of the lower capacitor electrode is connected to the circuit, while a second portion is not connected to the circuit. The high dielectric constant dielectric layer is located on the outer and inner sidewalls of the lower capacitor electrodes. The support structure connects to the top sidewall of each lower capacitor electrode and has a plurality of openings, and the top surface of the support structure does not have a high dielectric constant dielectric layer.

[0007] A capacitor detection method of the present invention includes providing a wafer, forming a detection structure in a dicing channel of the wafer, and then performing electron beam detection on the aforementioned detection structure. In the above method, the method of forming the detection structure includes: forming a circuit in the dicing channel of the wafer; sequentially forming at least one oxide layer and at least one silicon nitride layer on the dicing channel of the wafer; forming a plurality of vias in the oxide layer and the silicon nitride layer; a first portion of the plurality of vias exposing a portion of the circuit, and a second portion of the plurality of vias not exposing the circuit; then depositing a conductive material to cover the sides of the plurality of vias and the surface of the at least one silicon nitride layer. A plurality of openings are formed in the silicon nitride layer, exposing the oxide layer, wherein the remaining silicon nitride layer constitutes a support structure. Then the oxide layer is removed, and the conductive material on the top surface of the support structure is removed, wherein the remaining conductive material constitutes a plurality of lower electrodes for the capacitor for detection. A high dielectric constant layer is deposited on the outer and inner sidewalls of the support structure and the lower electrodes of multiple capacitors, and the high dielectric constant layer on the top surface of the support structure is etched away.

[0008] Based on the above, the high dielectric constant dielectric layer at the top of the capacitor detection structure of the present invention is removed, which can greatly reduce the noise of the detection background and thus improve the accuracy of identifying the defect location.

Implementation Method

[0009] Refer to Figure 1 and Figure 2. Figure 2 is a cross-sectional view of line segment II-II' of the capacitor detection structure in Figure 1.

[0010] The capacitor detection structure 10 includes a wafer 100 and a detection structure 200 located on the dicing track CL of the wafer 100. The detection structure 200 includes lines 202a-202b, a plurality of capacitor lower electrodes 204, a high dielectric constant dielectric layer 206, and a support structure 208. The lines 202a-202b are disposed in the dicing track CL of the wafer 100 and can be grounded. In some embodiments, line 202a includes a plurality of wires extending in the X direction, and line 202b includes a plurality of wires extending in the Y direction, thus enabling comprehensive detection of the electrical properties of the dense capacitor structure, thereby identifying structural defects 110. Multiple capacitor lower electrodes 204 are located on the dicing channel CL. The first portion 2041 of each capacitor lower electrode 204 is connected to lines 202a-202b, while the second portion 2042 is not connected. Therefore, electrons (e-) flow into the first portion 2041 connected to lines 202a-202b, while no electrons (e-) flow into the second portion 2042 not connected to lines 202a-202b. Since the detection structure 200 is designed to detect defects in the structure of a single electrode, the capacitor lower electrodes 204 are electrically separated from each other. However, it should be understood that the capacitor actually formed in the wafer may use all the capacitor lower electrodes 204 in Figure 1 as a single lower electrode, with a connecting line at the top 204t of each capacitor lower electrode 204. In another embodiment, the capacitor actually formed in the wafer may also use one or more capacitor lower electrodes 204 as a single lower electrode, as shown in Figure 1.

[0011] Referring to Figure 2, a high-dielectric-constant dielectric layer 206 is located on the outer sidewall s1 and inner sidewall s2 of the lower electrode 204 of the capacitor. The material of the high-dielectric-constant dielectric layer 206 is, for example, but not limited to, zirconium oxide, alumina, or other high-dielectric-constant dielectric materials. A support structure 208 connects to the top 204t sidewall of each lower electrode 204 of the capacitor and has multiple openings 210. The top surface 208s of the support structure 208 does not have the high-dielectric-constant dielectric layer 206. In some embodiments, if the lower electrode 204 has a considerable height, another support structure 212 can be added to the middle section of the lower electrode 204. However, the invention is not limited to this. In other embodiments, the support structure 212 can be omitted. Additionally, the top 204t of the lower electrode 204 has a height difference, and the support structure 208 is located on the higher portion of the top 204t of the lower electrode 204. Furthermore, the top surface s3 of the lower electrode 204 of the capacitor does not have the aforementioned high dielectric constant dielectric layer 206.

[0012] Referring again to Figure 1, in this embodiment, the top surface s3 of each capacitor lower electrode 204 is circular; each opening 210 of the support structure 208 is square, and the four corners of one opening 210 of the support structure 208 are aligned with the circular centers of the four capacitor lower electrodes 204. However, the present invention is not limited thereto. In other embodiments, the top surface s3 of the capacitor lower electrode 204 in the top view may be elliptical, square, or other shapes; the opening 210 in the top view may be circular, elliptical, or other shapes. Moreover, the relative positional relationship between the opening 210 and the capacitor lower electrode 204 can also be adjusted or changed as needed, and is not limited to that shown in Figure 1.

[0013] If a defect 110 such as a short circuit in the lower electrode 204 of an adjacent capacitor is caused by stress or other factors caused by the high dielectric constant dielectric layer 206, the detection structure 200 in FIG2 will generate secondary electrons in the second part 2042 that is not connected to the line 202b during the electron beam detection process, and a bright spot will be observed at that point.

[0014] Figure 3 is a flowchart of a capacitor detection method 300 according to a second embodiment of the present invention.

[0015] In step 302, a wafer is provided, and the wafer has dicing channels.

[0016] In step 304, a detection structure is formed on the dicing path of the wafer. The detection structure is mostly the same in size and process parameters as the capacitor actually formed in the wafer, but some processes or structures need to be adjusted to match the detection method. Detailed steps will be described below.

[0017] In step 306, the aforementioned inspection structure is subjected to electron beam inspection (EBI) in order to detect defects in the structure.

[0018] Figures 4A to 4F are schematic flowcharts of step 304 in the method of the second embodiment, wherein the same element symbols as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, which will not be repeated here.

[0019] Referring to FIG4A, a line 202b is formed in the dicing channel CL of the wafer 100, and then an oxide layer 400, a silicon nitride layer 402, an oxide layer 404 and a silicon nitride layer 406 are sequentially formed on the wafer 100, but not limited thereto. In other embodiments, the oxide layer 404 and the silicon nitride layer 406 may be omitted.

[0020] Referring to Figure 4B, multiple vias 408 are formed penetrating the oxide layer 400, silicon nitride layer 402, oxide layer 404, and silicon nitride layer 406. The first portion 4081 of the vias 408 exposes a portion of the circuit 202b, while the second portion 4082 of the multiple vias 408 does not expose the circuit 202b. Then, a conductive material 410 is deposited over the entire surface, covering the sides of the vias 408 and the surface of the silicon nitride layer 406.

[0021] Referring to Figure 4C, multiple openings 210 are formed in the silicon nitride layer 406 of Figure 4B to simultaneously remove part of the silicon nitride layer 406 in Figure 4B and expose part of the oxide layer 404, wherein the remaining silicon nitride layer becomes the support structure 208.

[0022] Then, referring to Figure 4D, all oxide layers, namely oxide layers 400 and 404 in Figure 4C, are removed using a wet process, leaving the remaining silicon nitride layer 402 as another support structure for the intermediate section. The aforementioned wet process, for example but not limited to, involves repeating the oxide removal process twice. Since the remaining support structure 208 surrounds the periphery of each capacitor lower electrode 204 as shown in Figure 1, it provides sufficient support. Next, the conductive material 410 on the top surface of the support structure 208 is removed to form multiple capacitor lower electrodes 204 for detection. The first portion 2041 of the capacitor lower electrode 204 is connected to the line 202b, while the second portion 2042 is not connected to the line 202b. Therefore, electrons e- flow into the first portion 2041 connected to the line 202b, while no electrons e- flow into the second portion 2042 not connected to the line 202b. After removing the oxide layers, an electron beam detection can be performed to check whether the multiple capacitor lower electrodes 204 on the cut track CL are in contact with each other or tilted. If the lower electrode 204 of the capacitor is defect-free, the electrons e- flowing from line 202b into the first part 2041 will be excited by the electron beam at the top 204t, producing secondary electrons and displaying a bright spot. The second part 2042, which is not connected to lines 202a-202b, will be dark. In other words, if an area that should have been detected as dark becomes bright, it indicates a defect at that location.

[0023] Next, referring to FIG4E, a high dielectric constant dielectric layer 206 is deposited on the outer sidewalls s1 and inner sidewalls s2 of the support structure 208, the support structure 212, and the multiple capacitor lower electrodes 204. In some embodiments, the high dielectric constant dielectric layer 206 is formed by, but not limited to, ALD, CVD, or other suitable deposition processes. The formation process of the high dielectric constant dielectric layer 206 will cause stress to the capacitor lower electrodes 204, which may lead to defects 110. If electron beam detection is performed directly after this step, it will be found that the top surface 208s of the entire support structure 208 is bright, and it is difficult to distinguish the location of the defect. This is because the support structure 208 has a high dielectric constant layer 206 on its surface, which is much larger than the top surface s3 of the lower electrode 204 of the capacitor. This high dielectric constant layer 206 has the characteristic of accumulating charge. Therefore, when the electron beam emitted during the electron beam detection process enters this large area of ​​high dielectric constant layer 206, it will accumulate in it and be excited by the subsequent electron beam to generate secondary electrons. Therefore, it is difficult to identify the location of the defect 110 from the bright background image.

[0024] Therefore, referring to FIG4F, the high dielectric constant layer 206 on the top surface 208s of the support structure 208 needs to be etched away. In some embodiments, the method of etching away the high dielectric constant layer 206 on the top surface 208s of the support structure 208 can use a time mode to control the termination of etching. In some embodiments, gases such as Cl2 (chlorine) and BCl3 (boron chloride) can be used to etch the high dielectric constant layer 206. Furthermore, before etching away the high dielectric constant layer 206 on the top surface 208s of the support structure 208, a patterned photoresist (not shown) can be formed on the wafer 100 outside the dicing CL to protect other structures. After etching away the high dielectric constant layer 206 on the top surface 208s of the support structure 208, an ashing and cleaning process can be performed to remove the patterned photoresist.

[0025] In the case that the top surface 208s of the support structure 208 does not have a high dielectric constant dielectric layer 206, the electron beam will not accumulate here. Therefore, after performing electron beam detection (step 306), the location of the defect 110 can be clearly identified from the dark background image.

[0026] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0027] Figure 1 is a top view of a capacitor detection structure according to a first embodiment of the present invention. Figure 2 is a cross-sectional view of a capacitor detection structure according to a first embodiment of the present invention. Figure 3 is a flowchart of a capacitor detection method according to a second embodiment of the present invention. Figures 4A to 4F are cross-sectional schematic diagrams of the manufacturing process for forming the detection structure in the method of the second embodiment.

Claims

1. A capacitor detection structure, comprising: A wafer with cleavage lines; The detection structure is disposed on the dicing channel of the wafer, wherein the detection structure includes: a circuit disposed in the dicing channel of the wafer; Multiple capacitor bottom electrodes are located on the dicing channel of the wafer, with a first portion of the multiple capacitor bottom electrodes connected to the circuit and a second portion of the multiple capacitor bottom electrodes not connected to the circuit; a high dielectric constant dielectric layer is located on the outer and inner sidewalls of the multiple capacitor bottom electrodes; and a support structure is connected to the top sidewall of each capacitor bottom electrode and has multiple openings, and the top surface of the support structure does not have the high dielectric constant dielectric layer.

2. The capacitor detection structure as claimed in claim 1, wherein the circuit includes a plurality of wires extending in the X direction and a plurality of wires extending in the Y direction.

3. The capacitor detection structure as claimed in claim 1, wherein the top of each lower electrode of the capacitor has a height difference, and the support structure is located on the higher portion of the top.

4. The capacitor detection structure as claimed in claim 3, wherein the top surface of each lower electrode of the capacitor does not have the high dielectric constant dielectric layer.

5. A capacitor detection method, comprising: Provide a chip; A detection structure is formed in the dicing groove of the wafer; The method for forming the detection structure includes: forming a circuit in the dicing channel of the wafer; and sequentially forming at least one oxide layer and at least one silicon nitride layer on the dicing channel of the wafer. A plurality of vias are formed in the at least one oxide layer and the at least one silicon nitride layer, with a first portion of the plurality of vias exposing a portion of the circuit and a second portion of the plurality of vias not exposing the circuit; a conductive material is deposited to cover the sides of the plurality of vias and the surface of the at least one silicon nitride layer; a plurality of openings are formed in the at least one silicon nitride layer, exposing a portion of the at least one oxide layer, wherein the remaining at least one silicon nitride layer forms a support structure; at least one oxide layer is removed; the conductive material on the top surface of the support structure is removed, wherein the remaining conductive material forms a plurality of lower electrodes for detection; a high dielectric constant layer is deposited on the outer and inner sidewalls of the support structure and the plurality of lower electrodes; and the high dielectric constant layer on the top surface of the support structure is etched away.

6. The capacitor detection method as claimed in claim 5, wherein the method for etching away the high dielectric constant dielectric layer on the top surface of the support structure is to use a time mode to control the termination of the etching.

7. The capacitor detection method as claimed in claim 6, further comprising, after removing the oxide layer, performing electron beam detection on the plurality of lower electrodes of the capacitor on the cut path.

8. The capacitor detection method as claimed in claim 7, wherein after performing the electron beam detection on the plurality of capacitor lower electrodes, the step of forming the high dielectric constant dielectric layer is performed.

9. The capacitor detection method as claimed in claim 5, further comprising forming a patterned photoresist on the wafer outside the dicing before etching away the high dielectric constant dielectric layer on the top surface of the support structure.

10. The capacitor testing method as claimed in claim 5, further comprising an ashing and cleaning process after etching away the high dielectric constant dielectric layer on the top surface of the support structure.

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