Pattern overlay correction for integrated circuit fabrication

Abstract

A method for integrated circuit (IC) fabrication, where the method includes providing a substrate including a first patterned layer and a second patterned layer, where the second patterned layer is aligned to the first patterned layer; measuring an overlay error of the second patterned layer with the first patterned layer across the substrate; based on the measuring, obtaining the overlay error of the second patterned layer with the first patterned layer; and exposing the second patterned layer to a first flux from a first location specific directional process to correct the overlay error.

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