Memory device and memory operation method

Abstract

A memory operation method, including: obtaining an operation code of a vector-matrix multiplication by a processing circuit, wherein the processing circuit is coupled to a memory array, and the memory array includes a plurality of memory strings; converting a first partition of multiple operation bits of the operation code into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and using the first conversion code and a second partition of the operation bits as an input data, and inputting the input data to the corresponding memory string, so that the memory strings generates an output signal according to a plurality of weight values.

Description

Technical Field

[0001] This disclosure relates to a memory operation method, and in particular to a memory device capable of performing product operations. Prior Technology

[0002] As computer processing speeds increase, the demands on memory speed and stability also rise. Given the diverse market demands, how to improve the application of memory so that it can not only read and write data but also function as part of computational processing has become a major challenge. Summary of the Invention

[0003] One aspect of this disclosure is a memory operation method, comprising: obtaining an operation code for vector matrix operations through a processing circuit, wherein the processing circuit is coupled to a memory array, the memory array includes a plurality of memory strings, and the operation code includes a plurality of operation bits; converting a first portion of the operation bits into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and inputting the first conversion code and a second portion of the operation bits as input data to a corresponding one of the memory strings, so that the memory strings generate an output signal according to a plurality of weight values. Accordingly, by splitting the operation code into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.

[0004] In one embodiment, the first portion includes the most significant bit of the operands. Since higher bits are more susceptible to transmission noise and thus cause greater errors, converting the most significant bit improves the noise reduction ratio during computation.

[0005] In one embodiment, the first portion of the operands is a higher bit compared to the second portion. As mentioned earlier, higher bits are more susceptible to transmission noise, resulting in greater errors; therefore, this approach improves the noise reduction ratio during computation.

[0006] In one embodiment, the number of bits in the first part accounts for 40% to 60% of the number of operands. Accordingly, the data transmission time can be effectively controlled.

[0007] In one embodiment, the number of bits in the first part is greater than the number of bits in the second part. Accordingly, converting the first part into a unary coding format will more clearly demonstrate the characteristics of unary coding and reduce noise interference.

[0008] In one embodiment, the number of bits in the first part accounts for 70% to 95% of the number of operands. Accordingly, the characteristics of unary coding can be more clearly utilized, and interference from noise can be reduced.

[0009] In one embodiment, the method of using the first conversion code and the second portion of the operands as input data further includes: converting the second portion of the operands into a second conversion code, wherein the format of the first conversion code is the same as the format of the second conversion code. Accordingly, the noise reduction ratio during computation can be effectively improved.

[0010] In one embodiment, the first conversion encoding is in unary encoding format. Unary encoding format can reduce noise interference during signal transmission.

[0011] In one embodiment, the operation encoding format is binary encoding. The binary encoding format will ensure transmission efficiency.

[0012] In one embodiment, the memory operation method further includes: receiving a plurality of output currents from the memory arrays; and calculating the total current value of the output currents to obtain an output signal. By summing the current values ​​of the memory arrays, vector matrix operations can be performed using the memory array.

[0013] Another embodiment of this disclosure is a memory device comprising a memory array, a sensing circuit, and a processing circuit. The memory array is coupled to a plurality of word lines and a plurality of bit lines, and includes a plurality of memory strings. The sensing circuit is coupled to the memory array to obtain an output signal from the memory array. The processing circuit is coupled to the memory array and is used to generate an operation code based on the operation data of a vector matrix operation, the operation code including a plurality of operation bits. The processing circuit is used to: convert a first portion of these operation bits into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and input the first conversion code and a second portion of the operation bits as input data to a corresponding memory string, so that the memory strings generate an output signal according to a plurality of weight values. Accordingly, by splitting the operation code into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.

[0014] In one embodiment, the first portion includes the most significant bit of the operands. Since higher bits are more susceptible to transmission noise and thus cause greater errors, converting the most significant bit improves the noise reduction ratio during computation.

[0015] In one embodiment, the first portion of the operands is a higher bit compared to the second portion. As mentioned earlier, higher bits are more susceptible to transmission noise, resulting in greater errors; therefore, this approach improves the noise reduction ratio during computation.

[0016] In one embodiment, the number of bits in the first part accounts for 40% to 60% of the number of operands. Accordingly, the data transmission time can be effectively controlled.

[0017] In one embodiment, the number of bits in the first part is greater than the number of bits in the second part. Accordingly, converting the first part into a unary coding format will more clearly demonstrate the characteristics of unary coding and reduce noise interference.

[0018] In one embodiment, the number of bits in the first part accounts for 70% to 95% of the number of operands. Accordingly, the characteristics of unary coding can be more clearly utilized, and interference from noise can be reduced.

[0019] In one embodiment, the processing circuit is further configured to convert a second portion of the operands into a second conversion code, wherein the format of the first conversion code is the same as that of the second conversion code. This effectively improves the noise reduction ratio during computation.

[0020] In one embodiment, the first conversion encoding is in unary encoding format. Unary encoding format can reduce noise interference during signal transmission.

[0021] In one embodiment, the operation encoding format is binary encoding. The binary encoding format will ensure transmission efficiency.

[0022] In one embodiment, the memory operation method further includes: receiving a plurality of output currents from the memory arrays; and calculating the total current value of the output currents to obtain an output signal. By summing the current values ​​of the memory arrays, vector matrix operations can be performed using the memory array. Simple Explanation of the Diagram

[0023] Figure 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure. Figure 2 is a schematic diagram of a memory string according to a portion of the embodiments disclosed herein. Figure 3A is a schematic diagram of the computational encoding according to some embodiments of the present disclosure. Figure 3B is a schematic diagram of the computational encoding according to some embodiments of the present disclosure. Figure 4 is a schematic diagram of the computational encoding according to some embodiments of the present disclosure. Figure 5 is a flowchart of a memory operation method according to some embodiments of the present disclosure. Figure 6 is a schematic diagram of a modified array according to some embodiments of the present disclosure. Figure 7A is a schematic diagram of the operation of a memory device according to some embodiments of the present disclosure. Figure 7B is a schematic diagram of the operation of a memory device according to some embodiments of the present disclosure. Implementation

[0024] The following drawings disclose several embodiments of the present invention. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0025] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0026] Figure 1 is a schematic diagram of a memory device 100 according to a partial embodiment of the present disclosure. The memory device 100 is used to implement an in-memory computing (IMC) architecture and can perform vector-matrix multiplication (VMM), such as the multiply-and-accumulate (MAC) operation commonly used in artificial intelligence technology.

[0027] The memory device 100 includes a memory array 110, a processing circuit 120, and a sensing circuit 130. The memory array 110 is coupled to the processing circuit 120 via multiple word lines and multiple bit lines, and includes multiple memory blocks BLK. Each memory block BLK contains multiple memory strings MR, and each memory string MR contains multiple memory cells (or unit cells). In one embodiment, the memory string MR is a NAND flash memory.

[0028] The processing circuit 120 is coupled to the memory array 110 via word lines and bit lines to provide relevant data for vector matrix operations. In one embodiment, the processing circuit 120 may be divided into a control circuit 121 and an encoding circuit 122. The control circuit 121 is used to provide initial data for vector matrix operations, and the encoding circuit 122 is used to encode this initial data for input to the memory array 110. The composition of the processing circuit 120 is not limited to the structure shown in Figure 1. In the following paragraphs, the execution of the processing circuit 120 can be performed by either the control circuit 121 or the encoding circuit 122.

[0029] When performing vector matrix operations, the processing circuit 120 provides the input values ​​(hereinafter referred to as "operation data") of the vector matrix operation to the memory array 110 through the word lines and bit lines, and the memory array 110 generates an output signal (such as output current) according to multiple internally preset weight values.

[0030] Sensing circuit 130 is coupled to memory array 110 to obtain an output signal from memory array 110. In one embodiment, sensing circuit 130 receives the output current of multiple memory arrays MR and calculates the total current value of all output currents to generate an output signal. In one embodiment, sensing circuit 130 also calculates the total impedance based on the total current as the output signal (i.e., the calculation result).

[0031] Figure 2 shows a partial schematic diagram of a memory string according to some embodiments of the present disclosure. Memory strings MR1 ​​to MRN can be applied to any one of the memory blocks BLK shown in Figure 1. The memory strings MR1 ​​to MRN shown in Figure 2 are two-dimensional structures, but in other embodiments, the memory block BLK may also contain a three-dimensional memory string structure.

[0032] Please refer to Figures 1 and 2. The memory arrays MR1 ​​to MRN contain multiple memory cells CA1 to CAP, CB1 to CBP, and CN1 to CNP, respectively, each with a specific weight value. Taking "multiplication-accumulation operation" as an example, the "weight value" can be the product coefficient used in artificial intelligence / neural networks. This "weight value" can be determined by the conductance (or impedance) value of each memory cell, and the conductance value of the memory cell depends on its threshold voltage. By applying voltage to each memory cell, the amount of charge in the floating gate can be controlled, thereby changing the threshold voltage.

[0033] Using the structure shown in Figure 2 as an example, the operation of the memory strings during vector matrix operations is further explained as follows: In one embodiment, the memory strings MR1~MRN receive read voltages through bit lines BL1~BLN, and simultaneously receive their respective operation data through their respective word lines WL11-1~WL1P-1, WL11-2~WL1P-2, and WL11-N~WL1P-N (e.g., word line WL11-1 provides operation data to memory cell CA1, and word line WL11-2 provides operation data to memory cell CB1). The memory strings MR1~MRN will generate cell currents according to internally set weight values, as well as the received read voltages and operation data. All cell currents will be output to the sensing circuit 130 through the common source line CSL to calculate the operation results. In one embodiment, the processing circuit 120 may generate an operation code (e.g., binary encoding) based on each operation data to serve as a digital voltage signal, details of which will be described in subsequent paragraphs.

[0034] In some embodiments, the aforementioned "weight values" can be divided into computational weight values, balancing weight values, and series weight values. The memory units CA1~CAP, CB1~CBP, and CN1~CNP in the memory array serve as computational weight units 210 and are each assigned a computational weight value. Each memory array may also include at least one balancing weight unit 220 and at least one series weight unit 230. The balancing weight unit 220 is used to adjust the equivalent impedance value of each memory array and can be used to adjust the standard deviation of the distribution of all weight values. The impedance of the series weight unit 230 depends on the overall impedance of each memory array, ensuring that each memory array has a basic impedance value. In other words, the balancing weight unit 220 and the series weight unit 230 are not directly used for multiplication operations, but rather to adjust the overall impedance of the memory array to make the computational results of the sensing circuit 130 more accurate.

[0035] Specifically, the computational weighting unit 210 and the balancing weighting unit 220 can be implemented using memory units of the same type, such as the transistor units CX1~CXQ, CY1~CYQ, and CZ1~CZQ shown in Figure 2. The balancing weighting units 220 in the memory array can also receive their respective setting signals through their respective word lines WL21-1~WL2Q-1, WL21-2~WL2Q-2, and WL21-N~WL2Q-N to set their respective balancing weight values. The series weighting units 230 can be implemented using impedance elements RS1~RSN (e.g., resistors) and can receive their respective setting signals through their respective word lines WL31~WL3N to set their respective series weight values.

[0036] To facilitate understanding, the input method of the "operation data" (i.e., the input values ​​of vector matrix operations) to the processing circuit 120 is described here. The processing circuit 120 converts the operation data into operation codes, and each operation code contains multiple operation bits. The processing circuit 120 inputs the operation codes into the corresponding memory strings for operation. For example, if the operation data for vector matrix operations contains multiple values ​​such as "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", then the processing circuit 120 can convert each operation data into a code of a specific format and apply a digital voltage signal to the corresponding memory string.

[0037] The operational codes generated by the processing circuit 120 can be represented by an encoding array. Figure 3A shows a schematic diagram of the encoding array 330A according to a partial embodiment of the present disclosure. In this embodiment, the operational data 310A is "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", and the processing circuit 120 converts the operational data 310A into a binary encoding format. For example, when the "9" in the operational data 310A is converted into a binary encoding format, the corresponding operational code 320A is "1, 0, 0, 1", containing four operational bits, and all operational codes can be organized into the encoding array 330A. During the operation, the processing circuit 120 inputs each operational bit in each operational code into the corresponding memory string column, using each column of the encoding array 330A as a unit.

[0038] However, due to the imperfect characteristics of electronic components and signal transmission noise, the calculation results of vector matrix operations will contain errors. Binary encoded data is highly sensitive to noise during computation, easily leading to excessively large errors in the results. Therefore, in some embodiments, the processing circuit 120 converts the computation data into a "Unary Code (or Thermometer Code)" format. This format reduces the problem of serious misinterpretation caused by slight transmission errors during computation data transmission.

[0039] The unary encoding format represents numerical values ​​using the "number of 1 bits". Therefore, even if a few bits are erroneous during data transmission, the actual value read will not differ significantly from the true value. Figure 3B shows a schematic diagram of the encoding array 330B according to a partial embodiment of this disclosure. In this embodiment, the operational data 310B is also "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", but the processing circuit 120 converts the operational data 310B into a unary encoding format. For example, when the "9" in the operational data 310B is converted into unary encoding, its operational encoding 320B is "0000000111111111", containing 9 encoding bits "1". All operational encodings 320B can be organized into an encoding array 330B, and each row of the encoding array 330B will correspond to one piece of operational data.

[0040] Taking the aforementioned embodiment as an example, when the computation is encoded in a unary coding format, the impact of transmission noise can be reduced by 5.68 times, thus reducing the error in the computation result. However, since the unary coding format has a large number of bits (e.g., 16 bits), it is also more time-consuming to transmit. In other words, the unary coding format has an advantage in dealing with noise, but a disadvantage in transmission time.

[0041] This disclosure divides the computational encoding into multiple parts for processing to balance noise reduction ratio and transmission efficiency. Figure 4 shows a schematic diagram of the computational encoding 400 according to a partial embodiment of this disclosure. The computational encoding 400 includes multiple operation bits A0 to A6. In one embodiment, the computational encoding 400 / operation bits A0 to A6 are in binary encoding format, but this disclosure is not limited thereto, and the processing circuit 120 can also organize the operation bits of the computational encoding 400 into octal, decimal, or hexadecimal formats.

[0042] The operands A0 to A6 can be divided into a first part 410 and a second part 420. For example, if the operation code is "1010011", then the first part 410 can be the first four operands A6 to A3 "1010", and the second part is the last three operands A2 to A0 "011". The number of bits contained in the first part 410 and the second part 420 can be set according to the requirements.

[0043] The processing circuit 120 converts the first part 410 into another format (such as unary encoding), while the second part 420 can retain its original format, or the processing circuit 120 can also convert the second part 420 into another format. Accordingly, by splitting the operation bits A0~A6 into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.

[0044] For example, the decimal arithmetic data "83" corresponds to the binary arithmetic code "1010011". If the complete arithmetic code "1010011" is directly converted to unary code format, it will have at least 83 bits (because it requires 83 "1"s). If the arithmetic code "1010011" is split into a first part 410 ("1010") and a second part 420 ("011"), the four arithmetic bits "1010" in the first part 410 correspond to the decimal value "10", that is, the unary code is "1111111111". Similarly, the three arithmetic bits "011" in the second part 420 correspond to the decimal value "3", that is, the unary code is "0000000111". Therefore, if the computation data is divided into two parts and converted into unary codes respectively, only a minimum of 13 bits (10 "1"s and 3 "1"s) are needed. It can be seen that splitting the computation bits A0~A6 into multiple parts can effectively reduce the time required for data transmission, that is, reduce the number of bits that need to be transmitted.

[0045] For ease of explanation, the memory operation method disclosed herein is illustrated in Figure 5. Referring to Figures 1, 4, and 5, in step S501, the processing circuit 120 obtains at least one piece of data for vector-matrix operations (e.g., "83"), and converts this data into an operation code 400, which includes multiple operation bits A0 to A6. In other embodiments, the processing circuit 120 may simultaneously generate multiple operation codes for multiple pieces of data.

[0046] In step S502, the processing circuit 120 divides the arithmetic bits A0 to A6 into multiple parts, such as the first part 410 and the second part 420 shown in Figure 4. In some embodiments, the number of bits contained in the first part 410 and the second part 420 can be adjusted as needed, and the method of splitting the arithmetic bits can be preset in the processing circuit 120.

[0047] In step S503, the processing circuit 120 converts the first part 410 into a first conversion code, and the format of the first conversion code is different from the format of the original operation code. For example, the binary code "1010" is converted into a unary code (i.e., 10 "1"s).

[0048] In step S504, the processing circuit 120 inputs the first conversion code and the second part 420 as input data into the memory string MR, so that the memory string MR generates an output signal according to multiple internally set weight values. The processing circuit 120 can selectively convert the second part 420, for example, it can maintain the binary encoding format or convert it to the unary encoding format.

[0049] When performing the aforementioned step S503, the processing circuit 120 can maintain the encoding format of the second part 420 (e.g., binary encoding). In other words, the input data in step S504 will contain encodings of multiple different encoding formats.

[0050] Continuing from the above, in other embodiments, when performing the aforementioned step S503, the processing circuit 120 can convert the second part 420 into a second conversion code, and the format of the second conversion code is the same as that of the first conversion code. For example, the binary arithmetic code "011" is converted into a unary code (i.e., three "1"s). In other words, all the encodings of the input data in step S504 will be in the same encoding format. Accordingly, the noise reduction ratio during operation can be effectively improved.

[0051] In some embodiments, the first portion 410 of the operands A0 to A6 includes the most significant bit (MSB). For example, if the operands A0 to A6 are "1010011", then the first portion 410 includes at least the most significant bit (i.e., the first "1" from the left). Since higher bits are more susceptible to errors caused by transmission noise, converting the most significant bit can improve the noise reduction ratio during computation.

[0052] In some embodiments, the first part 410 of operands A0 to A6 is a higher bit compared to the second part 420. Taking operands A0 to A6 as "1010011" as an example, the first part 410 consists of the first four operands "1010", and the second part 420 consists of the last three operands "011". In other words, each operand of the first part 410 is a higher bit than each operand of the second part 420. As mentioned earlier, higher bits are more susceptible to errors caused by transmission noise, thus this method can improve the noise reduction ratio during computation.

[0053] In some embodiments, the number of bits in the first part 410 and the second part 420 is similar. This allows for effective control of data transmission time. Taking the operands A0~A6 as "1010011" as an example, the number of bits in the first part 410 (4 bits) accounts for 40%~60% of all operands (7 bits). In other words, neither the first part 410 nor the second part 420 occupies an excessively large proportion. Therefore, even when both the first part 410 and the second part 420 are converted to a unary encoded format, the number of bits in each part after conversion will not be excessive, thus ensuring transmission speed and efficiency.

[0054] In other embodiments, the number of bits in the first part 410 is greater than the number of bits in the second part 420. Taking the operands A0~A6 as "1010011" as an example, the first six operands "101001" can be used as the first part, and the last operand "1" can be used as the second part. Accordingly, after converting the first part into a unary coding format, the characteristics of unary coding can be more clearly utilized, and noise interference can be reduced. In one embodiment, the number of bits in the first part accounts for 70% to 95% of all operands.

[0055] Please refer to Figures 1 and 3B. In some embodiments, the processing circuit 120 may adjust the encoding array 330B formed by the operational encoding 320B before executing the method in Figure 5, so that the distribution of bits "1" in the array is more even. If the distribution of bits "1" in the array is more even, the standard deviation of the memory string distribution will be smaller, and the calculation results of the sensing circuit 130 will be more accurate.

[0056] Figure 6 is a schematic diagram of a modified array 600 according to some embodiments of the present disclosure. In one embodiment, the processing circuit 120 is used to adjust the arrangement order of bits in each row of the encoding array 330B to reduce the distribution difference of bits "1" or bits "0" in the encoding array 330B. The adjusted encoding array 330B is the modified array 600.

[0057] Please refer to Figures 1, 3B, and 6. Specifically, the processing circuit 120 moves all "bit 1s" in the odd-numbered rows of the encoding array 330B in a first direction (e.g., to the right in Figure 3B); simultaneously, it moves all "bit 1s" in the even-numbered rows of the encoding array 330B in a second direction (e.g., to the left in Figure 3B). The first and second directions are opposite, thus generating the modified array 600. Accordingly, the degree of difference between each row of the modified array 600 will be less than the degree of difference between each row of the original encoding array 330B.

[0058] In some embodiments, the processing circuit can flexibly select the memory blocks to use based on the available space in the memory array 110. Referring to Figures 1, 7A, and 7B, Figures 7A and 7B show another embodiment of this disclosure, with Figure 7B presenting a simplified partial schematic diagram of the memory array 110. The memory array 110 is coupled to multiple bit lines (BLS) and contains multiple memory blocks (BLKS), which are located in multiple available regions 711-714, and available regions 711-712 are not adjacent to available regions 713-714. The processing circuit 120 can select multiple different available regions as computation regions to effectively utilize all the space within the memory array 110.

[0059] Continuing from the above, since the computation area contains multiple different available areas, before executing the memory operation method described in Figure 5, the processing circuit 120 divides the computation data D70 into multiple segments D71 to D74, and the number of segments corresponds to the number of available areas 711 to 714. Next, the processing circuit 120 sequentially provides the segments D71 to D74 to the memory array of memory blocks BLKS according to the index order of the multiple memory blocks BLKS in the available areas 711 to 714, to perform vector matrix operations.

[0060] The various components, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of textual description or graphical presentation in this disclosure.

[0061] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims defined in the appended patent application.

[0062] 100: Memory Device 110: Memory Array 120: Processing Circuit 121: Control Circuit 122: Encoding Circuit 130: Sensing Circuit 210: Computational Weight Unit 220: Balanced Weight Unit 230: Serial weighted unit 310A: Computational Data 320A: Operational Encoding 330A: Encoding Array 310B: Calculation Data 320B: Operational Encoding 330B: Encoded Array 400: Operation Code 410: Part One 420: Part Two 600: Modify Array 711-714: Available Areas A0-A6: Operands BL1-BLN: Bitline BLS: Bitline BLK: Memory Block BLKS: Memory Blocks CA1-CAP: Memory Unit CB1-CBP: Memory Unit CN1-CNP: Memory Unit CSL: Common Source Line CX1-CXQ: Transistor Unit CY1-CYQ: Transistor Units CZ1-CZQ: Transistor Unit D70: Calculation Data D71-D74: Section Data MR: Memory Serial MR1-MRN: Memory Serial RS1-RSN: Impedance element S501-S504: Steps WL11-1: Character Line WL12-1: Character Line WL13-1: Character Line WL1P-1: Character Line WL11-2: Character Line WL12-2: Character Line WL13-2: Character Line WL1P-2: Character Line WL11-N: Character Line WL12-N: Character Line WL13-N: Character Line WL1P-N: Character Line WL21-1: Character Line WL22-1: Character Line WL2Q-1: Character Line WL21-2: Character Line WL22-2: Character Line WL2Q-2: Character Line WL21-N: Character Line WL22-N: Character Line WL2Q-N: Character Line WL31-WL3N: Character Lines

[0063] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A memory operation method, comprising: obtaining an operation code for a vector matrix operation through a processing circuit, wherein the processing circuit is coupled to a memory array, the memory array comprising a plurality of memory strings, the operation code being generated based on operation data of the vector matrix operation, and the operation code comprising a plurality of operands; converting a first portion of the operands into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and inputting the first conversion code and a second portion of the operands as input data to a corresponding one of the memory strings, so that the memory strings generate an output signal according to a plurality of weight values, wherein the weight values ​​are set by a plurality of memory cells of the memory strings.

2. The memory operation method as described in claim 1, wherein the first portion includes the most significant bit of the operands.

3. The memory operation method as described in claim 2, wherein the first portion of the operand is a higher bit compared to the second portion.

4. The memory operation method as described in claim 1, wherein the number of bits in the first portion accounts for 40% to 60% of the number of operands.

5. The memory operation method as described in claim 1, wherein the number of bits in the first portion is greater than the number of bits in the second portion.

6. The memory operation method as described in claim 5, wherein the number of bits in the first portion accounts for 70% to 95% of the number of operands.

7. The memory operation method as claimed in claim 1, wherein the method of using the first conversion code and the second portion of the operands as the input data further comprises: converting the second portion of the operands into a second conversion code, wherein the format of the first conversion code is the same as the format of the second conversion code.

8. The memory operation method as described in claim 1, wherein the format of the first conversion encoding is unary encoding.

9. The memory operation method as described in claim 1, wherein the operation encoding is in binary encoding format.

10. The memory operation method as described in claim 1, further comprising: receiving a plurality of output currents from the memory arrays; and calculating a total current value of the output currents to obtain the output signal.

11. A memory device comprising: a memory array coupled to a plurality of word lines and a plurality of bit lines, and including a plurality of memory strings; a sensing circuit coupled to the memory array for acquiring an output signal from the memory array; and a processing circuit coupled to the memory array for generating an operation code based on operation data of a vector matrix operation, wherein the operation code includes a plurality of operation bits; wherein the processing circuit is further configured to: convert a first portion of the operation bits into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and input the first conversion code and a second portion of the operation bits as input data to a corresponding one of the memory strings, so that the memory strings generate the output signal according to a plurality of weight values, wherein the weight values ​​are set by a plurality of memory cells of the memory strings.

12. The memory device as claimed in claim 11, wherein the first portion includes the most significant bit of the operands.

13. The memory device as claimed in claim 12, wherein the first portion of the operands is a higher bit compared to the second portion.

14. The memory device as claimed in claim 11, wherein the number of bits in the first portion accounts for 40% to 60% of the number of operational bits.

15. The memory device as claimed in claim 11, wherein the number of bits in the first portion is greater than the number of bits in the second portion.

16. The memory device as claimed in claim 15, wherein the number of bits in the first portion accounts for 70% to 95% of the number of operational bits.

17. The memory device as claimed in claim 11, wherein the processing circuitry is further configured to: convert the second portion of the operands into a second conversion code, wherein the format of the first conversion code is the same as the format of the second conversion code.

18. The memory device as claimed in claim 11, wherein the format of the first conversion code is unary encoding.

19. The memory device as described in claim 11, wherein the operation encoding is in binary encoding format.

20. The memory device as claimed in claim 11, wherein the sensing circuit is further configured to: receive a plurality of output currents of the memory arrays; and calculate a total current value of the output currents to obtain the output signal.

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