Contention hint instruction

Abstract

An apparatus comprises instruction decoding circuitry configured to decode instructions of a program thread executed by a given processor core; and load / store control circuitry configured to select a target point of a memory system hierarchy at which to allocate data for a target cache line specified by a load / store instruction decoded by the instruction decoding circuitry. The load / store control circuitry is configured to select the target point of the memory system hierarchy depending on whether the load / store instruction is associated with a memory contention hint provided by a contention hint instruction decoded by the instruction decoding circuitry, the memory contention hint indicating that the target cache line is likely to be subject to contention for access from multiple threads of processing.

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