Scheme for increasing instruction throughput from central processing unit (CPU) to hardware accelerator

TW202634430APending Publication Date: 2026-08-16QUALCOMM INC
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Patent Information

Application Number
TW114147349
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-12-04
Filing Date
2025-12-03
Publication Date
2026-08-16

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Abstract

Certain aspects of the present disclosure provide techniques and apparatus for communicating scalable matrix extension (SME) requests to a hardware accelerator. Aspects include sending a first SME request to a buffer of a central processing unit. Aspects include sending a second SME request to the buffer. Aspects include merging the first SME request in the buffer and second SME request in the buffer to generate a request packet. Aspects include sending the request packet to the hardware accelerator.
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