Mark-dead instruction

Abstract

An apparatus comprises instruction decoding circuitry to decode instructions; processing circuitry to perform data processing in response to instructions decoded by the instruction decoding circuitry; and cache control circuitry to: set, in response to the instruction decoding circuitry decoding a mark-dead instruction specifying mark-dead target address information, one or more target cache lines selected based on the mark-dead target address information as a discardable cache line, wherein the discardable cache line is allowed to be discarded without data writeback even if the discardable cache line is dirty.

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