Adder circuit and method for operating the same

Abstract

A circuit is provided. The circuit comprises first and second plurality of tree structures of adders. The first plurality of tree structures perform additions of bits lower than a place value of a plurality of numbers. The adders in the first plurality of tree structures generate full swing outputs. The second plurality of tree structures of adders are coupled to the first plurality of tree structures of adders. The second plurality of tree structures perform additions of bits equal to or higher than the place value of the plurality of numbers. The second plurality of tree structures include transistors fewer than transistors of the first plurality of tree structures. One of the adders in the second plurality of tree structures generates a non full swing output in response to bits inputted to the adder in the second plurality of tree structures matching a pattern.

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