Flattened 2d network for neural network sparsification

Abstract

The present invention relates to a circuit including a plurality of routers arranged as a 2D flattened array, each router in the 2D flattened array comprises: a routing network configured to route data between the router and other routers in the 2D flattened array, an input interface configured to receive data from a memory, and an output interface configured to output data to the memory. The 2D flattened array implements a logical butterfly network, and is configurable as a gather circuit, operable to gather high-magnitude tensor data from a dense tensor into a condensed tensor, or a scatter circuit, operable to scatter tensor data from the condensed tensor into a sparse uncondensed tensor based on a given mask.

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