Spliced display

Abstract

A spliced display comprises a plurality of first display modules and at least one second display module. Each of the plurality of first display modules includes a first substrate, a first driving circuit, and a plurality of first pixels arranged on the first substrate, and the first driving circuit is electrically connected to the plurality of first pixels. Each of the at least one second display module includes a second substrate, a second driving circuit, and a plurality of second pixels arranged on the second substrate, and the second driving circuit is electrically connected to the plurality of second pixels. The second substrate is connected to at least one of the first substrate of the plurality of first display modules, and an arrangement density of the plurality of second pixels is greater than an arrangement density of the plurality of first pixels.

Description

[Technical Field]

[0001] This invention relates to a splicing display. [Previous Technology]

[0002] Light Emitting Diode (LED) display is a display technology that uses light-emitting diodes as a light source. It is widely used in electronic billboards, indoor and outdoor billboards, and high-resolution image simulation systems.

[0003] However, high-resolution light-emitting diode displays require a large number of tiny light-emitting elements to improve resolution, which increases the overall production cost, making it difficult to achieve both high resolution and low cost. [Summary of the Invention]

[0004] In view of the above, the present invention provides a splicing display.

[0005] A splicing display according to an embodiment of the present invention includes a plurality of first display modules and at least one second display module, wherein each of the plurality of first display modules includes a first carrier plate, a first driving circuit and a plurality of first pixels disposed on the first carrier plate, the first driving circuit being electrically connected to the plurality of first pixels, and each of the at least one second display module includes a second carrier plate, a second driving circuit and a plurality of second pixels disposed on the second carrier plate, wherein the second driving circuit is electrically connected to the plurality of second pixels, the second carrier plate is connected to the first carrier plate of at least one of the plurality of first display modules, and the arrangement density of the plurality of second pixels is greater than the arrangement density of the plurality of first pixels.

[0006] With the above structure, the splicing display disclosed in this case can use pixels with different arrangement densities on multiple carrier boards, and can achieve the goal of accommodating areas that require high image quality by splicing multiple carrier boards, and has a lower manufacturing cost compared to a single high-resolution image display.

[0007] The above description of the disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide a further explanation of the scope of the patent application of the present invention.

Implementation Method

[0009] The detailed features and advantages of the present invention are described below in the embodiments. The content is sufficient to enable anyone skilled in the art to understand the technical content of the present invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant objectives and advantages of the present invention. The following embodiments further illustrate the viewpoints of the present invention, but are not intended to limit the scope of the present invention in any way.

[0010] The following description of the video wall display is applicable to racing simulation or flight simulation, and the video wall display is composed of multiple display modules spliced ​​together, which has the advantages of scalability, flexibility and convenient maintenance.

[0011] Please refer to FIG1, which is a functional block diagram of a splicing display according to an embodiment of the present invention. As shown in FIG1, the splicing display 1A includes a plurality of first display modules 11 and at least one second display module 12. Each of the plurality of first display modules 11 includes a first carrier plate 111, a plurality of first pixels 112 and a first driving circuit 113, wherein the plurality of first pixels 112 and the first driving circuit 113 are disposed on the first carrier plate 111, and the first driving circuit 113 is electrically connected to the plurality of first pixels 112. In other embodiments, the first driving circuit 113 may be disposed on other substrates other than the first carrier plate 111. Each of the at least one second display module 12 includes a second carrier plate 121, a plurality of second pixels 122 and a second driving circuit 123, wherein the plurality of second pixels 122 and the second driving circuit 123 are disposed on the second carrier plate 121, and the second driving circuit 123 is electrically connected to the plurality of second pixels 122. In other embodiments, the second driving circuit 123 may be disposed on other substrates other than the second carrier board 121. The second carrier board 121 is connected to the first carrier board 111 of at least one of the plurality of first display modules 11. The connection includes direct connection and indirect connection. It should be noted that FIG1 is an exemplary illustration of the number and arrangement of the first display module 11, the first pixel 112, the second display module 12, and the second pixel 122, but the present invention is not limited thereto. In one embodiment, the number of second display modules 12 may be plurality. In particular, the arrangement density of the plurality of second pixels 122 in the second display module 12 is greater than the arrangement density of the plurality of first pixels 112 in the first display module 11, the image resolution of the second display module 12 is higher than that of the first display module 11, and the number of the plurality of second pixels 122 may depend on the requirements of the high-resolution image.

[0012] In this embodiment, each of the plurality of first display modules 11 has an independent first driving circuit 113 for driving a plurality of first pixels 112 disposed on a first carrier plate 111. For example, the first driving circuit 113 of each of the plurality of first display modules 11 can drive the plurality of first pixels 112 on each first carrier plate 111, and the first carrier plates 111 can be connected to each other or to the second carrier plate 121 of the second display module 12 to display a continuous image.

[0013] The second display module 12 has an independent second driving circuit 123 for driving a plurality of second pixels 122 with an arrangement density greater than that of a plurality of first pixels 112. For example, the second driving circuit 123 of each of the second display modules 12 can drive a plurality of second pixels 122 on each of the second carrier boards 121.

[0014] In this embodiment, the first display module 11 and / or the second display module 12 can be light-emitting diode display modules, and the first driving circuit 113 and the second driving circuit 123 can be light-emitting diode driving circuits, current driving circuits or pulse width modulation dimming circuits, each including a voltage regulator module and / or a current regulator.

[0015] Please refer to Figure 2, which is a functional block diagram of a splicing display according to another embodiment of the present invention. As shown in Figure 2, the splicing display 1B may include an image source 10, a plurality of first display modules 11, at least one second display module 12, a first image processor 13, a second image processor 14, a plurality of first driving circuit receivers 15 and a second driving circuit receiver 16, wherein each of the first display modules 11 includes a first carrier board 111, a plurality of first pixels 112 and a first driving circuit 113, and each of the second display modules 12 includes a second carrier board 121, a plurality of second pixels 122 and a second driving circuit 123. The implementation circuits / devices, functions and connection relationships in the first display modules 11 and the second display modules 12 are the same as those in the splicing display 1A of Figure 1, and will not be described in detail here. The first image processor 13 is connected to the image source 10 and multiple first drive circuit receivers 15. The multiple first drive circuit receivers 15 are respectively connected to their respective first drive circuits 113 in multiple first display modules 11. The second image processor 14 is connected to the image source 10 and second drive circuit receivers 16. The second drive circuit receivers 16 are connected to their respective second drive circuits 123 in the second display modules 12. The image source 10 can be considered as an internal component of the splicing display 1B or as an external component of the splicing display 1B. The first image processor 13 and the second image processor 14 can be referred to as controllers, sending cards, or timing controller (Tcon) ICs. The first driving circuit receiver 15 and the second driving circuit receiver 16 can be referred to as receiving cards. When the first image processor 13 and / or the second image processor 14 are timing control chips (Tcon ICs), the first driving circuit receiver 15 and the second driving circuit receiver 16 can be signal relay chips (Repeater ICs). The receivers or signal relay chips can be connected to one or more display modules (the first display module 11 and the second display module 12 shown in Figure 2).

[0016] The first image processor 13 receives the original image signal, down-converts the original image signal to generate a down-converted image signal, and transmits the down-converted image signal to multiple first display modules 11 via multiple first driving circuit receivers 15. The original image signal may be from the image source 10, such as a 4K Ultra High Definition (4K UHD) image with a resolution of 3840×2160 pixels, suitable for applications requiring high-quality output, such as multimedia playback, image processing, and professional design. The image down-conversion may refer to reducing the resolution of the input image signal from 3840×2160 pixels (4K UHD) to 1920×1080 pixels (Full HD). The resulting down-converted image signal can retain the main visual elements and be adaptively adjusted to a lower resolution for transmission to multiple first display modules 11.

[0017] The second image processor 14 is used to receive the original image signal and transmit the original image signal to the second display module 12 through the second drive circuit receiver 16. The original image signal received by the second image processor 14 can be the same as that of the first image processor 13, used to display a continuous image frame. The original image signal can be from the same image source 10, such as a 4K Ultra High Definition (4K UHD) image with a resolution of 3840×2160 pixels.

[0018] In this embodiment, the image source 10 may be a host or computer, or it may be an image signal from external software. The present invention is not limited thereto, and the image source 10 may simultaneously transmit separate image signals to the first image processor 13 and the second image processor 14.

[0019] Please refer to Figure 3, which is a schematic diagram of the pixel arrangement of the first and second display modules according to an embodiment of the present invention. Figure 3 shows a partial schematic diagram of the splicing display, which can be composed of multiple first display modules 11 and second display modules 12 as shown in Figure 3. As shown in Figure 3, the first display module 11 includes a first carrier plate 111, multiple first pixels 112a, 112b, 112c, 112d and a first driving circuit (not shown), and the second display module 12 includes a second carrier plate 121, multiple second pixels 122a, 122b, 122c, 122d and a second driving circuit (not shown). The connection relationship between the components and the implementing components are as described in the embodiment of Figure 1, and will not be repeated here. It should be noted that Figure 3 exemplarily shows the first carrier plate 111 and the second carrier plate 121 as quadrilaterals, but in other embodiments, the first carrier plate 111 and the second carrier plate 121 can each be other polygons (e.g., triangles). Figure 3 exemplarily illustrates the number and arrangement of a plurality of first pixels 112a, 112b, 112c, 112d and a plurality of second pixels 122a, 122b, 122c, 122d, but the present invention is not limited thereto. Specifically, the arrangement density of the plurality of second pixels 122a, 122b, 122c, 122d can be four times that of the arrangement density of the plurality of first pixels 112a, 112b, 112c, 112d, and the image resolution of the second display module 12 composed of the plurality of second pixels 122a, 122b, 122c, 122d is higher than that of the first display module 11 composed of the plurality of first pixels 112a, 112b, 112c, 112d.

[0020] In this embodiment, the spacing between any two adjacent first pixels is twice the spacing between any two adjacent second pixels 122a, 122b, 122c, 122d. For example, the arrangement of the multiple first pixels 112a, 112b, 112c, 112d and the multiple second pixels 122a, 122b, 122c, 122d can be as shown in Figure 3. The spacing PP1 between first pixels 112a and 112b and the spacing PP3 between first pixels 112a and 112c can be twice the spacing PP2 between second pixels 122a and 122b and the spacing PP4 between second pixels 122a and 122c. For example, each first pixel 112a, 112b, 112c, 112d can correspond to four second pixels and be aligned with one of the four second pixels, and each first pixel and second pixel can be equidistant in the horizontal and vertical directions.

[0021] Please refer to Figure 4, which is a schematic diagram of the pixel arrangement of the first and second display modules according to another embodiment of the present invention. Figure 4 shows a partial schematic diagram of the splicing display, which can be composed of multiple first and second display modules as shown in Figure 4. As shown in Figure 4, the first display module 11 includes a first carrier plate 111 and multiple first pixels 112e, 112f, 112g, 112h and a first driving circuit (not shown). The second display module 12 includes a second carrier plate 121, multiple second pixels 122e, 122f, 122g, 122h and a second driving circuit (not shown). The connection relationship between the components and the implementing components are as described in the embodiment of Figure 1, and will not be repeated here. It should be noted that Figure 4 exemplarily shows the first carrier plate 111 and the second carrier plate 121 as quadrilaterals, but in other embodiments, the first carrier plate 111 and the second carrier plate 121 can each be other polygons (e.g., triangles). Figure 4 exemplarily illustrates the number and arrangement of multiple first pixels 112e, 112f, 112g, 112h and multiple second pixels 122e, 122f, 122g, 122h, but the present invention is not limited thereto. Specifically, the arrangement density of the multiple second pixels 122e, 122f, 122g, 122h can be nine times that of the arrangement density of the multiple first pixels 112e, 112f, 112g, 112h, and the image resolution of the second display module 12 composed of the multiple second pixels 122e, 122f, 122g, 122h is higher than that of the first display module 11 composed of the multiple first pixels 112e, 112f, 112g, 112h.

[0022] In this embodiment, the spacing between any two adjacent first pixels 112e, 112f, 112g, 112h is three times the spacing between any two adjacent second pixels 122e, 122f, 122g, 122h. For example, the arrangement of the multiple first pixels 112e, 112f, 112g, 112h and the multiple second pixels 122e, 122f, 122g, 122h can be as shown in Figure 4. The spacing PP5 between the first pixel 112e and the first pixel 112f, and the spacing PP7 between the first pixel 112e and the first pixel 112g can be three times the spacing PP6 between the second pixel 122e and the second pixel 122f, and the spacing PP8 between the second pixel 122e and the second pixel 122g. For example, each first pixel 112e, 112f, 112g, 112h can correspond to nine second pixels and be aligned with one of the nine second pixels, and each first pixel and second pixel can be equidistant in the horizontal and vertical directions. In one embodiment, the spacing between multiple first pixels can be set to be greater than one times the spacing between second pixels and less than or equal to three times the spacing between multiple second pixels, in order to avoid excessive density differences between different pixel densities, causing discomfort to the human eye.

[0023] Please refer to Figures 5 and 6. Figure 5 is a schematic diagram of the enabled pixels of the second display module according to one embodiment of the present invention, and Figure 6 is a schematic diagram of the enabled pixels of the second display module according to another embodiment of the present invention. In one embodiment, the second driving circuit 123 of the second display module 12 shown in Figure 1 can drive to enable a portion of a plurality of second pixels 122 on the second carrier board 121 (hereinafter referred to as a plurality of used pixels). The plurality of used pixels (the second pixels 122i, 122j, 122k, 122l shown in Figure 5 or the second pixels 122m, 122n, 122o, 122p shown in Figure 6) can correspond to a plurality of first pixels of a plurality of first display modules 11 (the second pixels 122i, 122j, 122k shown in Figure 5). The relative positions of the first pixels 112a, 112b, 112c, 112d corresponding to 122l or the first pixels 112e, 112f, 112g, 112h corresponding to the second pixels 122m, 122n, 122o, 122p shown in FIG. 6 are such that the spacing between any two adjacent pixels among the plurality of used pixels is equal to the spacing between any two adjacent pixels among the plurality of first pixels 112, or the arrangement density of the plurality of used pixels on the second carrier plate 121 is equal to the arrangement density of the plurality of first pixels 112 on the first carrier plate 111. In other words, the second driving circuit 123 can turn off a portion of the plurality of second pixels 122 on the second carrier plate 121 according to the usage scenario, so that the spacing between any two adjacent pixels among the plurality of second pixels 122 is equal to the spacing between any two adjacent pixels among the plurality of first pixels 112, thereby reducing the power consumption of the display when used for general image purposes. For example, the image processor (the second image processor 14 shown in Figure 2) can store two different sets of parameter programs. For instance, the first set of parameter programs is used for all pixels, so all pixels receive a signal; the second set of parameter programs is used for some pixels, so unused pixels do not receive a signal. Specifically, the user can set the first or second set of parameter programs from the image processor (the second image processor 14 shown in Figure 2).

[0024] Please refer to Figure 7, which is a schematic diagram illustrating the arrangement of multiple display modules in a video wall display according to an embodiment of the present invention. As shown in Figure 7, the video wall display 1C may include multiple first display modules 11 and at least one second display module 12, wherein the second display module 12 is distributed in a first region A0 and the multiple first display modules 11 are distributed in a second region adjacent to the first region A0. The second display module 12 may be connected to the first display module 11, and the pixel arrangement density in the second display module 12 is greater than that in the first display module 11.

[0025] In this embodiment, when the splicing display 1C is used as an immersive racing simulation display, the second display module 12 can be set in the useful field of view area containing the vanishing point in the racing simulation. The vanishing point can be a point on the image plane of perspective rendering, where the two-dimensional perspective projections of mutually parallel lines in three-dimensional space can converge. In addition, the vanishing point can also be called a direction point, where lines with the same direction vector will have the same vanishing point. The useful field of view can be a visual area from which information can be obtained without eye or head movement, and the useful field of view will shrink as speed increases, especially in complex driving environments. In this embodiment, when the splicing display 1C is used as an immersive racing simulation display, since the useful field of view for driving shrinks as speed increases, the second display module 12 set in the useful field of view area A0 has a larger pixel density and can display high-resolution images to display the accurate vanishing point, while other areas are occupied by the first display module 11 with a smaller pixel density, which does not affect the driving senses because it is outside the useful field of view for driving.

[0026] Please refer to Figure 8, which is a schematic diagram illustrating the arrangement of multiple display modules in a splicing display according to another embodiment of the present invention. As shown in Figure 8, the splicing display 1D may include multiple first display modules 11 and multiple second display modules 12, wherein the second display modules 12 are distributed in multiple regions A1 and A2, and the multiple regions A1 and A2 are separated by the first display modules 11. The second display modules 12 may be connected to the first display modules 11, and the pixel density in the second display modules 12 is greater than that in the first display modules 11. In this embodiment, when the splicing display 1D is used for immersive flight simulation, the second display modules 12 may be set in a simulated head-up display (HUD) and / or a simulated driving instrument. In this embodiment, when the splicing display 1D is used as an immersive flight simulation display, the second display modules 12 set in the simulated head-up display and simulated driving instrument positions have a larger pixel density and can display high-resolution images.

[0027] With the above structure, the splicing display disclosed in this case can use pixels with different arrangement densities on multiple carrier boards, and can achieve the goal of accommodating areas that require high image quality by splicing multiple carrier boards, and has a lower manufacturing cost compared to a single high-resolution image display.

[0028] Although the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the present invention. Any modifications and refinements made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the appended claims. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a functional block diagram of a video wall display according to an embodiment of the present invention. Figure 2 is a functional block diagram of a video wall display according to another embodiment of the present invention. Figure 3 is a schematic diagram of the pixel arrangement of the first and second display modules according to an embodiment of the present invention. Figure 4 is a schematic diagram of the pixel arrangement of the first and second display modules according to another embodiment of the present invention. Figure 5 is a schematic diagram of the enabled pixels of the second display module according to an embodiment of the present invention. Figure 6 is a schematic diagram of the enabled pixels of the second display module according to another embodiment of the present invention. Figure 7 is a schematic diagram of the arrangement of multiple display modules of a video wall display according to an embodiment of the present invention. Figure 8 is a schematic diagram of the arrangement of multiple display modules of a video wall display according to another embodiment of the present invention.

Claims

1. A video wall display, comprising: a plurality of first display modules, each including a first carrier plate, a first driving circuit, and a plurality of first pixels disposed on the first carrier plate, wherein the first driving circuit is electrically connected to the first pixels; and at least one second display module, each including a second carrier plate, a second driving circuit, and a plurality of second pixels disposed on the second carrier plate, wherein the second driving circuit is electrically connected to the second pixels, the second carrier plate is connected to the first carrier plate of at least one of the first display modules, and the arrangement density of the second pixels is greater than the arrangement density of the first pixels.

2. The video wall as described in claim 1 further comprises: a plurality of first drive circuit receivers, respectively connected to the first display modules; a first image processor, connected to the first drive circuit receivers, for receiving an original image signal, down-converting the original image signal to generate a down-converted image signal, and transmitting the down-converted image signal through the first drive circuit receivers to the first display modules; at least one second drive circuit receiver, respectively connected to the at least one second display module; and a second image processor, connected to the at least one second drive circuit receiver, for receiving the original image signal and transmitting the original image signal through the at least one second drive circuit receiver to the at least one second display module.

3. The splicing display as claimed in claim 1, wherein the spacing between any two adjacent first pixels is two to three times the spacing between any two adjacent second pixels.

4. The splicing display as claimed in claim 1, wherein the arrangement density of the second pixels is four to nine times that of the arrangement density of the first pixels.

5. The video wall as claimed in claim 1, wherein the second driving circuit enables a plurality of used pixels among the second pixels, the spacing between any two adjacent used pixels being equal to the spacing between any two adjacent first pixels.

6. The video wall as claimed in claim 1, wherein the first carrier plate and the second carrier plate are each polygonal.

7. The video wall as claimed in claim 1, wherein the at least one second display module is distributed in a first region, and the first display modules are distributed in a second region adjacent to the first region.

8. The video wall as claimed in claim 1, wherein the number of the at least one second display module is multiple, the at least one second display module is distributed in multiple regions, and the regions are separated by the first display modules.

Images