Method of detecting sense margin of memory read operation and related sense margin detecting circuit

Abstract

During a first phase, a bit line voltage is transmitted to a first input end of a sense amplifier and a reference voltage is transmitted to a second input end of the sense amplifier, so that the sense amplifier output data according to a first voltage difference between its first and second input ends for providing a first data signal. During a second phase, the reference voltage is transmitted to the first input end of the sense amplifier and the bit line voltage is transmitted to the second input end of the sense amplifier, so that the sense amplifier output data according to a second voltage difference between its first and second input ends for providing a second data signal. During a third phase, a sense margin detecting signal is provided based on the first data signal and the second data signal.

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