Semiconductor memory devices

Abstract

This invention provides a memory capable of performing an update operation during a read or write operation. The memory includes a plurality of first data lines and a plurality of first control lines for writing, and a plurality of second data lines and a plurality of second control lines for reading. The memory cell includes: a first transistor, whose gate is connected to a first control line and one end is connected to a first data line; a second transistor, whose gate is connected to a second control line and one end is connected to a second data line; and a third transistor, whose gate is connected to the other end of the first transistor and one end is connected to the other end of the second transistor. The third data line corresponds to the plurality of first data lines, and the fourth data line corresponds to the plurality of second data lines. An input portion of a detection circuit is connected to the fourth data line. A holding circuit is disposed between the output portion of the detection circuit and the third data line. A fourth transistor is disposed between the output portion of the detection circuit and the third data line.

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