Memory circuit and method for operating the same

Abstract

A memory circuit includes a first memory array comprising a plurality of first memory cells, each of which is configured to operate with a first supply voltage; a second memory array comprising a plurality of second memory cells, each of which is configured to operate with a second supply voltage, the first supply voltage and the second supply voltage being different from each other; and a driver operatively coupled to the plurality of first memory cells and the plurality of second memory cells through a first access line and a second access line, respectively. The driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal.

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