Memory device and method for operating the same

Abstract

A memory device includes a plurality of memory cells, each of the plurality of memory cells comprising an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor; word lines; control gate lines; bit lines; read select lines; and write select lines. For each of the plurality of memory cells, the access transistor, the control gate transistor, and the resistive element are connected to one another in series, a gate terminal of the access transistor and a gate terminal of the control gate transistor are connected to first and second source / drain terminals of the read select transistor, respectively, and the gate terminal of the control gate transistor and a corresponding one of the control gate lines are connected to first and second source / drain terminals of the write select transistor, respectively.

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