Memory system, controller, and control method

TW202634617APending Publication Date: 2026-08-16KIOXIA CORP
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Patent Information

Application Number
TW114122200
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-02-10
Filing Date
2025-06-13
Publication Date
2026-08-16

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Abstract

Error correction is performed using a simpler configuration. The memory system includes: memory and a controller. The memory stores data encoded by error correction codes used to correct errors of t bits or less. The controller uses received characters read from the memory to calculate t checksums. By performing variable transformations on the checksums, it calculates (t-1) key information, which is used to obtain a first error pattern. This first error pattern includes a combination of multiple transformed positions obtained by performing variable transformations on multiple error positions when the number of error bits is (t+1). Using the corresponding information, it obtains the first error pattern corresponding to the key information. It performs inverse variable transformations on the transformed positions included in the first error pattern to calculate the error positions, and obtains a list containing a second error pattern, which includes combinations of error positions. It then performs list decoding using the list.
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