Semiconductor device, memory device, and forming method thereof

Abstract

A memory device may comprise a memory cell including first, second, third, fourth, fifth, sixth, and seventh transistors. The first to third transistors can be operatively formed from a first active region extending along a first lateral direction and each may have a respective gate structure extending along a second lateral direction. The fourth to seventh transistors can be operatively formed from a second active region extending along the first lateral direction and each may have a respective gate structure extending along the second lateral direction. The gate structures of the first to third transistors each may have a first measurement extending in the first lateral direction. The gate structures of the fourth to seventh transistors each may have a second measurement extending in the first lateral direction. The first measurement can be shorter than the second measurement.

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