Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure including a substrate structure and first device layers is provided. The first device layers are stacked on the substrate structure. The first device layers include semiconductor devices. Each of the semiconductor devices includes an active layer, a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is located on the active layer. The gate dielectric layer is located between the gate and the active layer. There is an air gap on one side of the gate dielectric layer. The air gap is located between the gate and the active layer. The first doped region and the second doped region are located in the active layer on two sides of the gate.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure having an air gap and a method for manufacturing the same. Prior Technology

[0002] Semiconductor components are widely used in electronic products. However, as the size of semiconductor components continues to shrink, further increasing the component density of semiconductor components remains a continuous goal. Summary of the Invention

[0003] This invention provides a semiconductor structure and its manufacturing method, which can effectively increase the device density of semiconductor devices.

[0004] This invention proposes a semiconductor structure including a substrate structure and multiple first element layers. The multiple first element layers are stacked on the substrate structure. Each first element layer includes multiple semiconductor elements. Each semiconductor element includes an active layer, a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is located on the active layer. The gate dielectric layer is located between the gate and the active layer. An air gap is present on one side of the gate dielectric layer. The air gap is located between the gate and the active layer. The first doped region and the second doped region are located in the active layer on both sides of the gate.

[0005] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate structure. Forming a plurality of first element layers on the substrate structure. Stacking the plurality of first element layers on the substrate structure. The plurality of first element layers include a plurality of semiconductor elements. Each semiconductor element includes an active layer, a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is located on the active layer. The gate dielectric layer is located between the gate and the active layer. An air gap is provided on one side of the gate dielectric layer. The air gap is located between the gate and the active layer. The first doped region and the second doped region are located in the active layer on both sides of the gate.

[0006] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, since multiple first element layers are stacked on the substrate structure, the element density of the semiconductor element can be effectively increased. Furthermore, when the semiconductor element is a one-transistor dynamic random access memory (1T-DRAM) element, since there is an air gap on one side of the gate dielectric layer, and the air gap is located between the gate and the active layer, the memory decision margin of the memory element can be improved.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figures 1A to 1O are flowcharts illustrating the manufacturing process of semiconductor structures according to some embodiments of the present invention. Implementation

[0009] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the perspective views and sectional views are not drawn to the same scale. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0010] Figures 1A to 1O are manufacturing process diagrams of semiconductor structures according to some embodiments of the present invention. Figures 1A to 1C and Figures 1L to 1O are perspective views. Figures 1D to 1K are cross-sectional views of the manufacturing process along section line I-I' in Figure 1C, wherein Figure 1D is a cross-sectional view of Figure 1C and Figure 1K is a cross-sectional view of Figure 1L.

[0011] Referring to FIG1A, a substrate structure 100 is provided. The substrate structure 100 may include a component layer 102 and a dielectric layer 104. In some embodiments, the component layer 102 may be a peripheral circuit component layer. The dielectric layer 104 is located on the component layer 102. In some embodiments, the material of the dielectric layer 104 is, for example, an oxide (e.g., silicon oxide).

[0012] In addition, an active material layer 106 may be provided. In some embodiments, the active material layer 106 may be made of a semiconductor substrate, such as a silicon substrate. In some embodiments, the active material layer 106 may have a first conductivity type (e.g., P-type). Hereinafter, the first conductivity type and the second conductivity type may be different conductivity types. In this embodiment, the first conductivity type may be P-type and the second conductivity type may be N-type, but the invention is not limited thereto. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. Furthermore, a dielectric layer 108 may be provided on one side of the active material layer 106. In some embodiments, the dielectric layer 108 may be made of an oxide (e.g., silicon oxide).

[0013] Referring to Figure 1B, dielectric layer 108 can be bonded to dielectric layer 104. In some embodiments, the bonding method between dielectric layer 108 and dielectric layer 104 is, for example, fusion bonding. In some embodiments, after bonding dielectric layer 108 to dielectric layer 104, the active material layer 106 can be thinned.

[0014] Referring to Figures 1C and 1D, the active material layer 106 can be patterned to form an active layer 106a. In some embodiments, the number of active layers 106a may be multiple, but the present invention is not limited thereto. As long as the number of active layers 106a is at least one, it falls within the scope of the present invention.

[0015] Referring to Figure 1E, a gate dielectric material layer 110 can be formed on the active layer 106a. In some embodiments, the material of the gate dielectric material layer 110 is, for example, a negative capacitance material. In some embodiments, the negative capacitance material is, for example, hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), yttrium aluminum garnet (YAG), aluminum nitride (AlN), hafnium aluminum oxide (HfAlO), hafnium silicate (HfSiO), or hafnium zirconium oxide (HfZrO). In some embodiments, the gate dielectric material layer 110 is formed by, for example, chemical vapor deposition.

[0016] Referring to Figure 1F, a gate material layer 112 can be formed on the gate dielectric material layer 110. In some embodiments, the material of the gate material layer 112 is, for example, doped polycrystalline silicon. In some embodiments, the gate material layer 112 is formed by, for example, chemical vapor deposition.

[0017] Referring to Figure 1G, the gate material layer 112 can be patterned to form the gate 112a. In some embodiments, the gate material layer 112 can be patterned using lithography and etching processes to form the gate 112a.

[0018] Referring to Figure 1H, a patterned photoresist layer 114 can be formed. The patterned photoresist layer 114 can expose the gate dielectric material layer 110 located on one side of the gate 112a. In some embodiments, the patterned photoresist layer 114 can be formed by a photolithography process.

[0019] Next, a patterned photoresist layer 114 can be used as a mask to remove part of the gate dielectric material layer 110, and an air gap AR1 is formed below the gate 112a. In some embodiments, the method for removing part of the gate dielectric material layer 110 is, for example, wet etching.

[0020] Referring to Figure 1I, the patterned photoresist layer 114 can be removed. In some embodiments, the removal method of the patterned photoresist layer 114 is, for example, dry stripping or wet stripping.

[0021] Next, a patterned photoresist layer 116 can be formed. The patterned photoresist layer 116 can expose the gate dielectric material layer 110 located on the other side of the gate 112a. In some embodiments, the patterned photoresist layer 116 can be formed by a photolithography process.

[0022] Then, using the patterned photoresist layer 116 as a mask, another portion of the gate dielectric material layer 110 can be removed to form the gate dielectric layer 110a. In some embodiments, the method for removing the other portion of the gate dielectric material layer 110 is, for example, dry etching.

[0023] Please refer to Figure 1J, where the patterned photoresist layer 116 can be removed. In some embodiments, the removal method of the patterned photoresist layer 116 is, for example, a dry stripping method or a wet stripping method.

[0024] Next, a dielectric layer 118 can be formed on the active layer 106a on both sides of the gate 112a. In some embodiments, the material of the dielectric layer 118 is, for example, an oxide (e.g., silicon oxide). In some embodiments, the dielectric layer 118 is formed by, for example, chemical vapor deposition.

[0025] Referring to Figures 1K and 1L, doped regions 120 and 122 can be formed in the active layer 106a on both sides of the gate 112a. In some embodiments, doped region 120 can be used as a source region and doped region 122 can be used as a drain region, but the present invention is not limited thereto. In other embodiments, doped region 120 can be used as a drain region and doped region 122 can be used as a source region. Furthermore, doped regions 120 and 122 may have a second conductivity type (e.g., N-type). In some embodiments, the method for forming doped regions 120 and 122 is, for example, ion implantation.

[0026] The semiconductor device T1 can be formed by the above method. In some embodiments, the semiconductor device T1 may include an active layer 106a, a gate 112a, a gate dielectric layer 110a, a doped region 120, and a doped region 122.

[0027] Referring to Figure 1M, a dielectric layer 124 can be formed on the other side of the active material layer 106. Thereby, dielectric layers 108 and 124 can be formed on the opposite side of the active layer 106a. In some embodiments, the material of the dielectric layer 124 is, for example, an oxide (e.g., silicon oxide). In some embodiments, the method for forming the dielectric layer 124 is, for example, chemical vapor deposition. In some embodiments, after forming the dielectric layer 124, a planarization process (e.g., chemical mechanical polishing) can be performed on the dielectric layer 124.

[0028] Using the above method, a device layer DL1 can be formed on the substrate structure 100. In some embodiments, the device layer DL1 may include a semiconductor device T1, a dielectric layer 108, a dielectric layer 124, and a dielectric layer 118.

[0029] Referring to FIG1N, the steps of bonding the dielectric layer 108 on another active material layer 106 to the dielectric layer 124 of the element layer DL1, as well as the steps of FIG1C to FIG1M, can be repeated to form a plurality of element layers DL1 on the substrate structure 100. The plurality of element layers DL1 are stacked on the substrate structure 100. In some embodiments, the method of bonding the dielectric layer 108 on another active material layer 106 to the dielectric layer 124 of the element layer DL1 is, for example, a fusion bonding method.

[0030] Referring to Figure 10, conductive pillars 126 can be formed in multiple element layers DL1. The conductive pillars 126 are electrically connected to multiple doped regions 120. Furthermore, conductive pillars 128 can be formed in multiple element layers DL1. The conductive pillars 128 are electrically connected to multiple doped regions 122. In some embodiments, the materials of the conductive pillars 126 and 128 are, for example, tungsten or copper. In some embodiments, the conductive pillars 126 and 128 can be formed using an interconnect process.

[0031] Next, a wire 130 can be formed on the conductive post 126. The wire 130 is electrically connected to the conductive post 126. A wire 132 is formed on the conductive post 128. The wire 132 is electrically connected to the conductive post 128. In some embodiments, the wire 130 can be used as a source line and the wire 132 can be used as a bit line, but the invention is not limited thereto. In other embodiments, the wire 130 can be used as a bit line and the wire 132 can be used as a source line. In some embodiments, the materials of the wires 130 and 132 are, for example, aluminum or copper. In some embodiments, the wires 130 and 132 can be formed by an interconnect process.

[0032] Furthermore, although not shown in the figure, the required dielectric layer can be formed on multiple component layers DL1, and conductive pillars 126, conductive pillars 128, wires 130 and 132 can be located in the above dielectric layer, the description of which is omitted here.

[0033] The semiconductor structure 10 of the above embodiment will be described below with reference to FIG1K, FIG1L and FIG1O. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0034] Referring to Figures 1K, 1L, and 1O, the semiconductor structure 10 includes a substrate structure 100 and a plurality of device layers DL1. In some embodiments, the substrate structure 100 may include a device layer 102 and a dielectric layer 104. The dielectric layer 104 is located on the device layer 102. The plurality of device layers DL1 are stacked on the substrate structure 100. The plurality of device layers DL1 include a plurality of semiconductor devices T1. In some embodiments, each device layer DL1 includes a plurality of semiconductor devices T1. The plurality of semiconductor devices T1 in each device layer DL1 may be arranged in a direction parallel to the top surface of the substrate structure 100. In some embodiments, the semiconductor device T1 may be a Fin Field-Effect Transistor (FinFET). Each semiconductor device T1 includes an active layer 106a, a gate 112a, a gate dielectric layer 110a, a doped region 120, and a doped region 122. The gate 112a is located on the active layer 106a and may intersect with the active layer 106a. A gate dielectric layer 110a is located between the gate 112a and the active layer 106a. In some embodiments, the material of the gate dielectric layer 110a is, for example, a negative capacitance material. In some embodiments, the negative capacitance material is, for example, hafnium dioxide, zirconium dioxide, aluminum oxide, yttrium aluminum garnet, aluminum nitride, hafnium aluminum oxide, hafnium silicate, or hafnium zirconium oxide. An air gap AR1 is provided on one side of the gate dielectric layer 110a. The air gap AR1 is located between the gate 112a and the active layer 106a. Doped regions 120 and 122 are located in the active layer 106a on both sides of the gate 112a.

[0035] In some embodiments, each element layer DL1 may further include a dielectric layer 108 and a dielectric layer 124. Dielectric layers 108 and 124 are located on opposite sides of the active layer 106a. In some embodiments, the dielectric layer 108 of one of two adjacent element layers DL1 may be bonded to the dielectric layer 124 of the other adjacent element layer DL1. In some embodiments, the dielectric layer 108 of the element layer DL1 closest to the substrate structure 100 may be bonded to the substrate structure 100. In some embodiments, the dielectric layer 108 of the element layer DL1 closest to the substrate structure 100 may be bonded to the dielectric layer 104. In some embodiments, each element layer DL1 may further include a dielectric layer 118. The dielectric layer 118 is located between the dielectric layer 124 and the doped region 120 and between the dielectric layer 124 and the doped region 122. The dielectric layer 118 is further located on both sides of the doped region 120 and the doped region 122. In some embodiments, the dielectric layer 118 may seal the air gap AR1. In some embodiments, in a single element layer DL1, the dielectric layer 124 may fill the space between two adjacent semiconductor elements T1.

[0036] In some embodiments, the semiconductor structure 10 may further include conductive pillars 126 and 128. Conductive pillar 126 is located in a plurality of element layers DL1. Conductive pillar 126 is electrically connected to doped region 120. Conductive pillar 128 is located in a plurality of element layers DL1. Conductive pillar 128 is electrically connected to doped region 122. In some embodiments, the semiconductor structure 10 may further include wires 130 and 132. Wire 130 is located on conductive pillar 126. Wire 130 is electrically connected to conductive pillar 126. Wire 132 is located on conductive pillar 128. Wire 132 is electrically connected to conductive pillar 128.

[0037] Furthermore, the details of each component in the semiconductor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be described again here.

[0038] As can be seen from the above embodiments, in the semiconductor structure 10 and its manufacturing method, since multiple element layers DL1 are stacked on the substrate structure 100, the element density of the semiconductor element T1 can be effectively increased. Furthermore, when the semiconductor element T1 is a single-transistor dynamic random access memory (1T-DRAM) element, since there is an air gap AR1 on one side of the gate dielectric layer 110a, and the air gap AR1 is located between the gate 112a and the active layer 106a, the memory decision margin of the memory element can be improved.

[0039] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0040] 10: Semiconductor Structure 100: Base structure 102, DL1: Component layer 104, 108, 118, 124: Dielectric layers 106: Active Material Layer 106a: Active Layer 110: Gate dielectric material layer 110a: Gate dielectric layer 112: Gate material layer 112a: Gate 114, 116: Patterned photoresist layers 120, 122: Doped regions 126, 128: Conductive pillars 130, 132: Conductors AR1: Air gap T1: Semiconductor components

Claims

1. A semiconductor structure, comprising: Substrate structure; The substrate structure includes a plurality of first element layers stacked on the substrate structure, wherein the plurality of first element layers include a plurality of semiconductor elements, wherein each semiconductor element includes: an active layer; a gate located on the active layer; a gate dielectric layer located between the gate and the active layer, wherein an air gap is provided on one side of the gate dielectric layer and the air gap is located between the gate and the active layer; and a first doped region and a second doped region located in the active layer on both sides of the gate, wherein each first element layer further includes: a first dielectric layer and a second dielectric layer located on opposite sides of the active layer; and a third dielectric layer located between the second dielectric layer and the first doped region and between the second dielectric layer and the second doped region, wherein the third dielectric layer seals the air gap.

2. The semiconductor structure as claimed in claim 1, wherein the material of the gate dielectric layer includes a negative capacitance material.

3. The semiconductor structure as claimed in claim 2, wherein the negative capacitor material comprises hafnium dioxide, zirconium dioxide, aluminum oxide, yttrium aluminum garnet, aluminum nitride, hafnium aluminum oxide, hafnium silicate, or hafnium zirconium oxide.

4. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer of one of two adjacent first element layers is bonded to the second dielectric layer of the other of two adjacent first element layers.

5. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer of the first element layer closest to the substrate structure is bonded to the substrate structure.

6. The semiconductor structure as claimed in claim 1, wherein in a single first element layer, the second dielectric layer fills the space between two adjacent semiconductor elements.

7. The semiconductor structure as claimed in claim 1, wherein the third dielectric layer is further located on both sides of the first doped region and the second doped region.

8. The semiconductor structure as claimed in claim 1, wherein the substrate structure comprises: Second component layer; And a third dielectric layer, located on the second element layer, wherein the first dielectric layer of the first element layer closest to the substrate structure is bonded to the third dielectric layer.

9. The semiconductor structure as described in claim 1, further comprising: The first conductive pillar is located in one of the multiple first element layers and is electrically connected to the first doped region; And a second conductive pillar, located in a plurality of the first element layers, and electrically connected to the second doped region.

10. The semiconductor structure as described in claim 9, further comprising: A first wire is located on the first conductive post and is electrically connected to the first conductive post; And a second wire, located on the second conductive post and electrically connected to the second conductive post.

11. The semiconductor structure of claim 1, wherein each of the first element layers includes a plurality of the semiconductor elements, and the plurality of semiconductor elements in each of the first element layers are arranged in a direction parallel to the top surface of the substrate structure.

12. A method for manufacturing a semiconductor structure, comprising: Provide the base structure; The substrate structure includes a plurality of first element layers stacked on the substrate structure, each first element layer comprising a plurality of semiconductor elements, and each semiconductor element comprising: an active layer; a gate located on the active layer; a gate dielectric layer located between the gate and the active layer, wherein an air gap is present on one side of the gate dielectric layer and the air gap is located between the gate and the active layer; and a first doped region and a second doped region located in the active layer on both sides of the gate, wherein each first element layer further comprises: a first dielectric layer and a second dielectric layer located on opposite sides of the active layer; and a third dielectric layer located between the second dielectric layer and the first doped region and between the second dielectric layer and the second doped region, wherein the third dielectric layer seals the air gap.

13. A method for manufacturing a semiconductor structure as claimed in claim 12, wherein the method for forming each of the semiconductor elements comprises: A gate dielectric material layer is formed on the active layer; A gate material layer is formed on the gate dielectric material layer; The gate material layer is patterned to form the gate; a first patterned photoresist layer is formed, wherein the first patterned photoresist layer exposes the gate dielectric material layer located on one side of the gate; using the first patterned photoresist layer as a mask, a portion of the gate dielectric material layer is removed, and the air gap is formed below the gate; Remove the first patterned photoresist layer; form a second patterned photoresist layer, wherein the second patterned photoresist layer exposes the gate dielectric material layer located on the other side of the gate; using the second patterned photoresist layer as a mask, remove another portion of the gate dielectric material layer to form the gate dielectric layer; and remove the second patterned photoresist layer.

14. A method for manufacturing a semiconductor structure as claimed in claim 13, wherein a portion of the gate dielectric material layer removal method comprises a wet etching method, and another portion of the gate dielectric material layer removal method comprises a dry etching method.

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