Flash memory device and method for forming the same

Abstract

A flash memory device a method for forming the same are provided. The flash memory device includes a substrate, a semiconductor stacked structure, and isolation features. The semiconductor stacked structure is disposed on the substrate. The semiconductor stacked structure includes a first floating gate and a second floating gate. The isolation features are disposed in the substrate so that the semiconductor stacked structure is sandwiched between the isolation features. The isolation feature includes a first dielectric filling layer, a second dielectric liner layer, and a third dielectric filling layer. The first dielectric filling layer is located at a lower portion of the isolation feature. The second dielectric liner conformally covers the first dielectric filling layer. The third dielectric filling layer is located on an upper portion of the isolation feature. The first dielectric filling layer and the third dielectric filling layer are formed of a first material, the second dielectric liner is formed of a second material, and the second material is different from the first material.

Description

[Technical Field]

[0001] This invention relates to a flash memory device and a method for forming the same, and particularly to an isolation component of a NAND type flash memory device and a method for forming the same. [Previous Technology]

[0002] To increase the component density within flash memory devices and improve their overall performance, manufacturing technologies continue to strive towards miniaturization of component size. However, flash memory manufacturing technology faces some new challenges in the miniaturization process. Therefore, it is urgent to overcome the various problems that arise. [Summary of the Invention]

[0003] Embodiments of the present invention provide a flash memory device, including a substrate, a semiconductor stack structure, and a plurality of isolation components. The semiconductor stack structure is disposed on the substrate. The semiconductor stack structure includes a first floating gate and a second floating gate. The second floating gate is disposed on the first floating gate. The isolation components are disposed in the substrate and extend beyond the substrate, such that the semiconductor stack structure is sandwiched between the isolation components. Each isolation component includes a first dielectric filling layer, a second dielectric liner, and a third dielectric filling layer. The first dielectric filling layer is located at the lower part of the isolation component. The second dielectric liner conformably covers the first dielectric filling layer. The third dielectric filling layer is located at the upper part of the isolation component, such that the second dielectric liner is sandwiched between the first dielectric filling layer and the third dielectric filling layer. The first dielectric filling layer and the third dielectric filling layer are formed of a first material, and the second dielectric liner is formed of a second material, wherein the second material is different from the first material.

[0004] Embodiments of the present invention provide a method for forming a flash memory device, including providing a substrate; forming a semiconductor stack structure and a plurality of isolation components on the substrate. The isolation components protrude from the substrate such that the semiconductor stack structure is sandwiched between the isolation components. The semiconductor stack structure includes a first floating gate and a second floating gate. The second floating gate is disposed on the first floating gate. Forming each isolation component includes forming a first dielectric filling layer in the substrate adjacent to the semiconductor stack structure. A first top surface of the first dielectric filling layer is recessed in a second top surface of the semiconductor stack structure; a second dielectric pad material layer is compliantly formed on the semiconductor stack structure and the first top surface of the first dielectric filling layer; a third dielectric filling material layer is formed on the second dielectric pad material layer; and a portion of the second dielectric pad material layer and a portion of the third dielectric filling material layer are removed to expose a plurality of second side surfaces of the second floating gate. The first and third dielectric filling layers are formed of a first material, and the second dielectric pad material layer is formed of a second material, wherein the second material is different from the first material.

Implementation Method

[0005] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the present invention. The present disclosure may also be implemented in various different ways, and is not limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements.

[0006] In the conventional flash memory manufacturing process, the isolation components in the source / drain regions of the flash memory device located in the array region have recesses of different depths in areas with different pattern densities, causing word line disturbance (WL disturb) and affecting the electrical performance and reliability of the final flash memory device. Therefore, a flash memory and its formation method are needed to solve the aforementioned problems.

[0007] Figures 1A-8A and 1B-8B are cross-sectional schematic diagrams of positions 10 and 20 with different pattern densities in the array region of the flash memory device 500 at various process stages. In some embodiments, position 10 is a position with a higher pattern density, and position 20 is a position with a lower pattern density. For example, position 10 may be the position of a semiconductor stack structure 250 (Figure 8A) with a floating gate and a control gate, and position 20 may be the position between adjacent semiconductor stack structures 250. In Figures 1A, 1B and subsequent figures, directions 100, 110 and 120 are shown as the x direction, y direction and z direction, respectively. In addition, directions 100 and 110 are directions substantially parallel to the top surface 200T of the substrate 200, and may also be referred to as the word line (width) direction and bit line (length) direction of the flash memory device 500, respectively. Direction 120 is a direction substantially perpendicular to the top surface 200T of the substrate 200 (may also be referred to as the longitudinal direction 120).

[0008] As shown in Figures 1A and 1B, a substrate 200 is provided. The substrate 200 may include an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate, a gallium arsenide substrate, a gallium phosphide substrate, an indium phosphide substrate, an indium arsenide substrate, and / or an indium antimonide substrate; or an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or combinations thereof. In one embodiment, the substrate 200 may be an insulator-coated silicon substrate. In this embodiment, the substrate 200 is a silicon substrate.

[0009] Next, a plurality of tunneling dielectric layers 202, a plurality of semiconductor stacked structures 220, and a plurality of isolation structures 230R1 are formed on the substrate 200 at the location 10 where the floating gate is provided, and a plurality of masking patterns 216 and a plurality of isolation structures 230 are formed on the substrate 200 at the location 20 where the floating gate is not provided. The semiconductor stacked structure 220 may be formed by forming a tunneling dielectric material layer (not shown) and a semiconductor stacked layer (not shown) including a masking material layer on the substrate 200 at the location 10, and forming a masking material layer on the substrate 200 at the location 20. Next, a patterned mask is used and an etching process is employed to etch the tunneling dielectric material layer and semiconductor stack layer at location 10 and the masking material layer at location 20 to form a plurality of trenches (not shown) in the substrate 200. The semiconductor stack layer at location 10 is divided by the trenches into a plurality of tunneling dielectric layers 202 and a plurality of semiconductor stack structures 220, and the masking material layer at location 20 is divided by the trenches into a plurality of masking patterns 216. In some embodiments, the etching process for forming the semiconductor stack structure 220 (or masking pattern 216) may include anisotropic etching processes, such as dry etching processes.

[0010] A tunneling dielectric layer 202 is disposed on the substrate 200 and sandwiched between the substrate 200 and the semiconductor stack structure 220. In some embodiments, the tunneling dielectric layer 202 may include oxides, nitrides, oxynitrides, or combinations thereof. For example, the tunneling dielectric layer 202 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. In this embodiment, the tunneling dielectric layer 202 is, for example, silicon oxide. In some embodiments, the tunneling dielectric layer 202 may be formed using a deposition process or a thermal oxidation process.

[0011] The semiconductor stacked structure 220 and the isolation structure 230R1 in position 10 are staggered in direction 100, and the masking pattern 216 and the isolation structure 230 in position 20 are staggered in direction 100. Furthermore, the isolation structures 230 and 230R1 protrude from the substrate, such that the semiconductor stacked structure 220 in position 10 is sandwiched between the isolation structures 230R1 in direction 100, and the masking pattern 216 in position 200 is sandwiched between the isolation structures 230 in direction 100.

[0012] As shown in Figure 1A, the semiconductor stack structure 220 sequentially includes a floating gate 210 and a mask pattern 216 from bottom to top. In some embodiments, the floating gate 210 includes a first floating gate 206L disposed on the tunneling dielectric layer and a second floating gate 206U disposed on the first floating gate 206L. The first floating gate 206L may not have doped material, and the second floating gate 206U may have doped material. In some embodiments, the floating gate 210 may include a conductive material. For example, the floating gate 210 may be doped or undoped polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, or a combination thereof. For example, the first floating gate 206L may be undoped polycrystalline silicon, and the second floating gate 206U may be doped polycrystalline silicon. In some embodiments, the dopant may include N-type or P-type dopant, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (BF3+). In this embodiment, the dopant is P-type to increase the number of electrons controlled by the subsequent control gate. In some embodiments, a deposition process may be used to form the floating gate 210.

[0013] In some embodiments, the mask pattern 216 includes an oxide layer 212O and a nitride layer 212N. The mask pattern 216 can be used as an etching mask for the etching process of forming the tunneling dielectric layer 202 and the floating gate 210 to protect the underlying film layer from the process.

[0014] In some embodiments, the oxide layer 212O comprises an oxide, such as tetraethyl orthosilicate (TEOS) oxide. In some embodiments, the nitride layer 212N comprises a nitride, such as silicon nitride (SiN) or silicon oxynitride (SiON). As shown in Figures 1A and 1B, the masking patterns 216 at positions 10 and 20 may have the same structure.

[0015] After forming the semiconductor stack structure 220 at position 10 and the mask pattern 216 at position 20, isolation structures 230R1 and 230 are formed at positions 10 and 20 of the substrate 200. The formation of the isolation structures 230R1 and 230 may include: performing a deposition process to deposit dielectric pad material layers (not shown) and dielectric fill material layers (not shown) in a plurality of trenches of adjacent semiconductor stack structures 220 at position 10 and adjacent mask patterns 216 at position 20. Next, a removal process is performed to remove excess dielectric pad material layers and dielectric fill material layers from the top surfaces of the semiconductor stack structures 220 at position 10 and the mask pattern 216 at position 20 to form a plurality of isolation structures 230 at positions 10 and 20. Afterward, a patterning process may be performed to etch the isolation structures 230 at position 10 to form isolation structure 230R1 at position 10 and to form an opening O1 between the semiconductor stack structures 220. In some embodiments, the patterning process for forming the isolation structures 230R1, 230 may include an anisotropic etching process, such as a dry etching process. The removal process may include a planarization process or the aforementioned etching process. The aforementioned planarization process may include chemical mechanical polishing (CMP).

[0016] An isolation structure 230R1 is formed in a substrate 200 adjacent to the semiconductor stack structure 220, which defines the active region in position 10 (located on both sides of the isolation structure 230R1). Furthermore, an isolation structure 230 is formed in a substrate 200 adjacent to the mask pattern 216, which defines the active region in position 20 (located on both sides of the isolation structure 230). In some embodiments, isolation structures 230 and 230R1 may be single-layer or multi-layer structures. In this embodiment of the invention, isolation structures 230 and 230R1 are multi-layer structures. For example, isolation structure 230R1 has a dielectric substrate 224R1 and a dielectric filling layer 226R1 disposed on the dielectric substrate 224R1, and isolation structure 230 has a dielectric substrate 224 and a dielectric filling layer 226 disposed on the dielectric substrate 224.

[0017] As shown in Figure 1A, a dielectric liner 224R1 is formed in a substrate 200 adjacent to the semiconductor stack structure 220. The dielectric liner 224R1 surrounds the dielectric fill layer 226R1 and is adjacent to the tunneling dielectric layer 202 and the opposite side of the floating gate 210. The top surface 230R1T of the isolation structure 230R1 is recessed in the top surface 220T of the semiconductor stack structure 220. For example, the top surface 230R1T of the isolation structure 230R1 (including the top surface of the dielectric fill layer 226R1) is a concave arcuate surface. In some embodiments, the lowest point of the concave arcuate surface (top surface 230R1T) is located above the top surface 206LT of the first floating gate 206L and below the top surface 210T of the floating gate 210 (i.e., the top surface of the second floating gate 206U).

[0018] As shown in Figure 1B, a dielectric liner 224 is formed in a substrate 200 adjacent to the mask pattern 216. The dielectric liner 224 surrounds the dielectric fill layer 226 and is adjacent to the opposite side of the mask pattern 216. The top surface 230T of the isolation structure 230 is aligned with the top surface 216T of the mask pattern 216.

[0019] In some embodiments, the isolation structures 230, 230R1 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicone glass, borosilicate glass, fluorinated silicate glass, undoped silicate glass, organosilicon glass, SiOxCy, spin-coated glass, tetraethoxysilane, low dielectric constant dielectric materials, or combinations thereof. In some embodiments, the dielectric substrate 224 and dielectric filling layer 226 of the isolation structure 230 and the dielectric substrate 224R1 and dielectric filling layer 226R1 of the isolation structure 230R1 comprise the same material, such as silicon oxide.

[0020] It should be noted that the pattern density at position 10 is higher than that at position 20. The spacing P2 of the mask pattern 216 at position 20 is greater than the spacing P1 of the semiconductor stack structure 220 at position 10, therefore the shapes exhibited by the isolation structures 230 and 230R1 will also be slightly different. For example, as shown in Figure 1A, the isolation structure 230R1 at position 10 has a larger depth-to-width ratio, producing a teardrop-like profile. In contrast, as shown in Figure 1B, the isolation structure 230 at position 20 has a smaller depth-to-width ratio, producing a trapezoidal profile (i.e., wider at the bottom).

[0021] Next, a deposition process such as atomic layer deposition (ALD) can be performed to compliantly form a dielectric spacer layer 234 on the semiconductor stack structure 220, the mask pattern 216, and the isolation structures 230R1 and 230. The dielectric spacer layer 234 covers the top surface 220T and part of the side surface of the semiconductor stack structure 220, the top surface 216T of the mask pattern 216, the top surface 230R1T of the isolation structure 230R1, and the top surface 230T of the isolation structure 230.

[0022] In some embodiments, the dielectric spacer layer 234 and the dielectric liner 224 and dielectric fill layer 226 of the isolation structure 230 and the dielectric liner 224R1 and dielectric fill layer 226R1 of the isolation structure 230R1 comprise the same material, such as silicon oxide.

[0023] Next, as shown in Figures 2A and 2B, an etching process, such as reactive ion etching (RIE), can be performed to etch the isolation structures 230R1 and 230 in positions 10 and 20, and to remove the dielectric spacer layer 234. The etching process etches the dielectric filling layer 226R1 and the dielectric liner layer 224R1 from the opening O1 in position 10, exposing the opposite side 206US of the second floating gate 206U (or completely exposing the opposite side 206US of the second floating gate 206U). In position 10, the etched isolation structure (including the dielectric filling layer and the dielectric liner layer) is designated as isolation structure 230R1' (including the dielectric filling layer 226R1' and the dielectric liner layer 224R1').

[0024] In addition, the dielectric filling layer 226 and dielectric liner 224 in the above-mentioned etching process recessed position 20 form an opening O2 between the mask pattern 216. In position 20, the etched isolation structure (including the dielectric filling layer and dielectric liner) is marked as isolation structure 230R2 (including dielectric filling layer 226R2 and dielectric liner 224R2).

[0025] In some embodiments, the top surface 230R1'T of the etched isolation structure 230R1' is a concave arc-shaped surface. This concave arc-shaped surface may intersect with the opposite side surface 206LS of the first floating gate 206L, and may partially expose the opposite side surface 206LS of the first floating gate 206L. Furthermore, the lowest point of the concave arc-shaped surface is located above the top surface 202T of the tunneling dielectric layer 202 and below the top surface of the first floating gate 206L. In some embodiments, the etched dielectric filling layer 226R1' (or isolation structure 230R1') may partially cover the opposite side surface 206LS of the first floating gate 206L.

[0026] Since the spacing P2 of the mask pattern 216 at position 20 is greater than that of the semiconductor stack structure 220 at position 10, the opening O2 formed in the isolation structure 230R2 is shallower.

[0027] Next, a cleaning process is performed on the intermediate structure of the process. In some embodiments, the isolation structures 230R1' and 230R2 may be further annealed to strengthen the isolation structures 230R1' and 230R2.

[0028] Next, as shown in Figures 3A and 3B, a deposition process such as atomic layer deposition (ALD) can be performed to compliantly form a dielectric pad material layer 236 on the top surface 220T of the semiconductor stacked structure 220, the top surface 216T of the mask pattern 216, the top surface 230R1'T of the isolation structure 230R1', and the top surface 230R2T of the isolation structure 230R2 in positions 10 and 20.

[0029] The dielectric pad material layer 236 covers the dielectric substrates 224R1' and 224R2 and the dielectric filler layers 226R1' and 226R2, and is adjacent to the opposite side 206US of the second floating gate 206U. Furthermore, in position 10, the dielectric substrate 224R1' and the dielectric pad material layer 236 are adjacent to different portions of the side 206LS of the first floating gate 206L. It should be noted that the dielectric pad material layer 236 does not completely fill the openings O1 and O2.

[0030] In some embodiments, the dielectric pad material layer 236 comprises a nitride, such as silicon nitride (SiN) or silicon oxynitride (SiON). In some embodiments, the material of the dielectric pad material layer 236 differs from the materials of the dielectric substrate 224R1' and dielectric fill layer 226R1' of the isolation structure 230R1' and the dielectric substrate 224R2 and dielectric fill layer 226R2 of the isolation structure 230R2. The material of the dielectric pad material layer 236 may be the same as the material of the nitride layer 212N. For example, the dielectric substrate 224R1' and dielectric fill layer 226R1' of the isolation structure 230R1' and the dielectric substrate 224R2 and dielectric fill layer 226R2 of the isolation structure 230R2 are formed of silicon oxide, while the dielectric pad material layer 236 and the nitride layer 212N are formed of silicon nitride. Furthermore, the interface between the dielectric pad material layer 236 and the nitride layer 212N, which are formed from the same material, is not obvious.

[0031] Next, as shown in Figures 4A and 4B, a deposition process such as spin-coated glass (SOG) can be performed to form a dielectric filling material layer (not shown) over the dielectric pad material layer 236. The dielectric filling material layer completely fills the openings O1 and O2 and covers the semiconductor stack structure 220, the mask pattern 216, the isolation structures 230R1' and 230R2, and the dielectric pad material layer 236.

[0032] Next, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove a portion of the dielectric filling material layer and dielectric pad material layer 236 on the top surface 220T of the semiconductor stack structure 220 and the top surface 216T of the mask pattern 216 until the top surface 220T of the semiconductor stack structure 220 and the top surface 216T of the mask pattern 216 are exposed, so that a dielectric pad material layer 236-1 and a dielectric filling material layer 238-1 are formed in the opening O1 between the semiconductor stack structures 220, and a dielectric pad material layer 236-2 and a dielectric filling material layer 238-2 are formed in the opening O2 between the mask patterns 216. After the planarization process described above, the top surface 220T of the semiconductor stacked structure 220 and the top surface 216T of the mask pattern 216 can be flush with the top surface 238-1T of the dielectric filling material layer 238-1 and the top surface 238-2T of the dielectric filling material layer 238-2.

[0033] After the above process, a plurality of isolation components 240-1 can be formed in position 10, and a plurality of isolation components 240-2 can be formed in position 20. The isolation component 240-1 includes, from bottom to top, an isolation structure 230R1', a dielectric pad material layer 236-1, and a dielectric fill material layer 238-1. The isolation component 240-2 includes, from bottom to top, an isolation structure 230R2, a dielectric pad material layer 236-2, and a dielectric fill material layer 238-2.

[0034] Next, as shown in Figures 5A and 5B, an etching process, such as dry etching, can be performed to remove a portion of the dielectric pad material layer 236-1 and a portion of the dielectric fill material layer 238-1 of the isolation member 240-1 at position 10, exposing the opposite side 206US of the second floating gate 206U, thereby forming an isolation member 240-1R including an isolation structure 230R1', a dielectric pad layer 236-1R, and a dielectric fill layer 238-1R. Furthermore, at position 20, a portion of the dielectric pad material layer 236-2 and all of the dielectric fill material layer 238-2 of the isolation member 240-2 are removed, thereby forming an isolation member 240-2R including an isolation structure 230R2 and a dielectric pad layer 236-2R. Because the etch selectivity ratios of dielectric pad material layers 236-1 and 236-2 and dielectric filling material layers 238-1 and 238-2 are different, after the above etching process, the top surface 238-1RT of the dielectric filling layer 238-1R can be lower than the top surface 236-1RT of the dielectric pad layer 236-1R. Furthermore, the above etching process can form openings O3 between the semiconductor stacked structures 220 at position 10 and openings O4 between the mask patterns 216 at position 20. The top surface 236-1RT of the dielectric liner 236-1R can be aligned with the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L), or the top surface 236-1RT of the dielectric liner 236-1R can be located below the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L).

[0035] In some embodiments, the dielectric filling layer 238-1R may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicone glass, borosilicate glass, fluorinated silicate glass, undoped silicate glass, organosilicon glass, SiOxCy, spin-coated glass, tetraethoxysilane, low dielectric constant dielectric material, or a combination thereof. In some embodiments, the dielectric filling layer 238-1R, the dielectric substrate 224R1' of the isolation structure 230R1', the dielectric filling layer 226R1', and the dielectric substrate 224R2 and dielectric filling layer 226R2 of the isolation structure 230R2 comprise the same material, such as silicon oxide.

[0036] In some embodiments, the above etching process includes a selective etching process, which can control the etching selectivity of the etching process so that the etching rate of the dielectric filling material layers 238-1 and 238-2 (formed of silicon oxide) shown in Figures 4A and 4B is greater than the etching rate of the dielectric pad material layers 236-1 and 236-2 (formed of silicon nitride).

[0037] It should be noted that the pattern density at position 10 is higher than that at position 20. Therefore, the etching processes shown in Figures 5A and 5B will have different etching rates at positions 10 and 20. At this time, the dielectric pad material layer 236-1 of the isolation member 240-1 and the dielectric pad material layer 236-2 of the isolation member 240-2 shown in Figures 4A and 4B can be used as etching stop layers for the above-mentioned etching process to control the degree of concavity of the isolation members 240-1R and 240-2R at positions 10 and 20 after the etching process. For example, the lowest point of the top surface 240-2RT (concave arc surface) of the isolation member 240-2R at position 20 will not be lower than the lowest point of the dielectric pad layer 236-1R. In this embodiment of the invention, by forming isolation components 240-1 and 240-2 with a three-layer structure including silicon oxide / silicon nitride / silicon oxide (ONO), the above-mentioned patterning process can avoid the excessive depth difference of the isolation components in the regions (positions 10 and 20) with different pattern densities in the array region, thereby improving the character line interference problem.

[0038] Next, as shown in Figures 6A and 6B, a multi-pass etching process including dry etching and wet etching can be performed to remove the mask pattern 216 (including oxide layer 212O and nitride layer 212N) at positions 10 and 20, exposing the top surface 210T of the floating gate 210 at position 10 and the top surface 200T of the substrate 200 at position 20. This etching process may remove portions of the dielectric liner 236-1R, 236-2R and dielectric fill layer 238-1R from openings O3 and O4.

[0039] Next, as shown in Figures 7A and 7B, a deposition process can be performed to compliantly form a gate dielectric layer 242 on the isolation components 240-1R, 240-2R, and the floating gate 210. The gate dielectric layer 242 may cover the top surface of the isolation component 240-1R, but does not fill the opening O3 between the floating gates 210. The gate dielectric layer 242 may cover the dielectric substrate 236-2R of the isolation component 240-2R, but does not fill the opening O4 between the substrates 200. In one embodiment, the gate dielectric layer 242 includes silicon oxide, silicon nitride, silicon oxynitride, or a three-layer structure including silicon oxide / silicon nitride / silicon oxide (ONO).

[0040] Next, as shown in Figures 8A and 8B, a deposition process can be performed to form a control gate layer 246 on the gate dielectric layer 242. The control gate layer 246 fills the opening O3 between the floating gates 210 at position 10 and the opening O4 between the substrate 200 at position 20. In some embodiments, the control gate layer 246 includes a polysilicon or other conductive material layer. After the above process, a flash memory device 500 is formed.

[0041] As shown in Figure 8A, the flash memory device 500 includes a substrate 200, a semiconductor stack structure 250, and a plurality of isolation components 240-1R. The semiconductor stack structure 250 is disposed on the substrate 200. The semiconductor stack structure 250 includes a tunneling dielectric layer 202 and a floating gate 210 (including a first floating gate 206L and a second floating gate 206U). The first floating gate 206L is disposed on the tunneling dielectric layer 202. The second floating gate 206U is disposed on the first floating gate 206L. The isolation components 240-1R are disposed in the substrate 200 adjacent to the semiconductor stack structure 250 and extend in direction 120 protruding from the substrate 200, so that the semiconductor stack structure 250 is sandwiched between the isolation components 240-1R. The isolation component 240-1R includes a dielectric filling layer 226R1', a dielectric liner 236-1R, and a dielectric filling layer 238-1R. The dielectric filling layer 226R1' is located at the lower portion 240-1L of the isolation component 240-1R. The dielectric liner 236-1R conformably covers the dielectric filling layer 226R1'. The dielectric filling layer 238-1R is located at the upper portion 240-1U of the isolation component 240-1R, such that the dielectric liner 236-1R is sandwiched between the dielectric filling layer 226R1' and the dielectric filling layer 238-1R. In some embodiments, the dielectric filling layer 226R1' and the dielectric filling layer 238-1R are formed of a first material, and the dielectric liner 236-1R is formed of a second material, and the second material is different from the first material. In some embodiments, the first material includes an oxide, and the second material includes a nitride.

[0042] In some embodiments, the top surface 236-1RT of the dielectric liner 236-1R is aligned with the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L), or the top surface 236-1RT of the dielectric liner 236-1R is located below the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L). In other words, the top surface 236-1RT of the dielectric liner 236-1R is not higher than the interface between the first floating gate 206L and the second floating gate 206U (i.e., the top surface 206LT of the first floating gate 206L). In some embodiments, the top surface of the isolation member 240-1R includes the top surface 236-1RT of the dielectric liner 236-1R and the top surface 238-1RT of the dielectric filler layer 238-1R.

[0043] In the isolation component 240-1R, the interface between the dielectric filling layer 226R1' and the dielectric liner 236-1R is a concave arc-shaped surface, and the lowest point of the concave arc-shaped surface is located above the top surface 202T of the tunneling dielectric layer 202.

[0044] In the isolation component 240-1R, the dielectric liner 236-1R covers the opposite side 206LS of the first floating gate 206L, and the opposite side 206US of the second floating gate 206U can be exposed from the dielectric liner 236-1R.

[0045] In some embodiments, the isolation member 240-1R may further include a dielectric liner 224R1'. The dielectric liner 224R1' surrounds the dielectric fill layer 226R1' and is adjacent to the side 202S of the tunneling dielectric layer 202 and the side 206LS of the first floating gate 206L. In some embodiments, the tunneling dielectric layer 202 and the first floating gate 206L may be separated from the dielectric liner 236-1R by the dielectric liner 224R1', or the dielectric liner 224R1' and the dielectric liner 236-1R may be adjacent to different portions of the side 206LS of the first floating gate 206L. In some embodiments, the dielectric liner 224R1' is formed of a first material, such as an oxide.

[0046] The flash memory device 500 further includes a gate dielectric layer 242 and a control gate layer 246. The gate dielectric layer 242 is formed on the isolation member 240-1R and the floating gate 210. The control gate layer 246 is formed on the gate dielectric layer 242. In some embodiments, the gate dielectric layer 242 is adjacent to the dielectric fill layer 238-1R and the dielectric liner layer 236-1R.

[0047] Although the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0048] To make the features and advantages of the present invention more apparent and understandable, different embodiments are described below in detail with reference to the accompanying drawings: Figures 1A to 8A and 1B to 8B are partial cross-sectional schematic diagrams of each process stage of the method for forming a flash memory device according to some embodiments of the present invention.

Claims

1. A flash memory device, comprising: One base; A semiconductor stack structure is disposed on a substrate, wherein the semiconductor stack structure includes: a first floating gate; and a second floating gate disposed on the first floating gate; and a plurality of isolation members disposed in the substrate and extending out of the substrate such that the semiconductor stack structure is sandwiched between the isolation members, wherein each isolation member includes: a first dielectric filling layer located at a lower portion of the isolation member; a second dielectric liner conformably covering the first dielectric filling layer; and a third dielectric filling layer located at an upper portion of the isolation member, such that the second dielectric liner is sandwiched between the first dielectric filling layer and the third dielectric filling layer, wherein the first dielectric filling layer and the third dielectric filling layer are formed of a first material, and the second dielectric liner is formed of a second material, and the second material is different from the first material, wherein a first top surface of each isolation member includes a third top surface of the third dielectric filling layer and a second top surface of the second dielectric liner.

2. The flash memory device as claimed in claim 1, wherein the second top surface of the second dielectric liner of each isolation component is aligned with or located below a first interface between the first floating gate and the second floating gate.

3. The flash memory device as claimed in claim 1, wherein the first material comprises an oxide and the second material comprises a nitride.

4. The flash memory device as described in claim 1, further comprising: A tunneling dielectric layer is sandwiched between the substrate and the semiconductor stack structure, wherein a second interface between the first dielectric filling layer and the second dielectric substrate is a concave arc-shaped surface, and the lowest point of the concave arc-shaped surface is located above the tunneling dielectric layer.

5. The flash memory device as claimed in claim 1, wherein the second dielectric liner covers a plurality of first sides of the first floating gate.

6. The flash memory device as claimed in claim 1, wherein a third top surface of the third dielectric fill layer of each of the isolation components is lower than a second top surface of the second dielectric substrate.

7. The flash memory device as described in claim 4, wherein each of the isolation components further comprises: A fourth dielectric liner surrounds the first dielectric filler layer and is adjacent to a plurality of third sides of the tunneling dielectric layer and a plurality of first sides of the first floating gate, wherein the fourth dielectric liner is formed of the first material.

8. The flash memory device as claimed in claim 7, wherein the second dielectric liner and the fourth dielectric liner are adjacent to different portions of the first sidewalls of the first floating gate.

9. The flash memory device as described in claim 1, further comprising: A gate dielectric layer is formed on the isolation components and the floating gate; And a control gate layer is formed on the gate dielectric layer.

10. The flash memory device as claimed in claim 9, wherein the gate dielectric layer is adjacent to the third dielectric fill layer and the second dielectric liner.

11. A method for forming a flash memory device, comprising: Provide a base; A semiconductor stack structure and a plurality of isolation components are formed on the substrate, wherein the isolation components protrude from the substrate so that the semiconductor stack structure is sandwiched between the isolation components, wherein the semiconductor stack structure includes: a first floating gate; and a second floating gate disposed on the first floating gate; wherein forming each isolation component includes: forming a first dielectric filling layer in the substrate adjacent to the semiconductor stack structure, wherein a first top surface of the first dielectric filling layer is recessed into a second top surface of the semiconductor stack structure; and compliantly forming a second dielectric pad material layer on the semiconductor stack structure and the first top surface of the first dielectric filling layer; A third dielectric filler layer is formed on the second dielectric pad material layer; and a portion of the second dielectric pad material layer and a portion of the third dielectric filler layer are removed to expose a plurality of second sides of the second floating gate to form a second dielectric liner and a third dielectric filler layer for each of the isolation components, wherein a top surface of each isolation component includes a top surface of the third dielectric filler layer and a top surface of the second dielectric liner, wherein the first dielectric filler layer and the third dielectric filler layer are formed of a first material, the second dielectric pad material layer is formed of a second material, and the second material is different from the first material.

12. A method of forming a flash memory device as claimed in claim 11, wherein before forming the second dielectric pad material layer, the first top surface of the first dielectric filler layer is a concave arcuate surface, and the lowest point of the concave arcuate surface is located below a third top surface of the first floating gate.

13. A method of forming a flash memory device as claimed in claim 11, wherein the second dielectric pad material layer is adjacent to a plurality of first sides of the first floating gate.

14. A method of forming a flash memory device as claimed in claim 11, wherein a fourth top surface of the second dielectric pad material layer is aligned with or located below a first interface between the first floating gate and the second floating gate.

15. The method of forming a flash memory device as described in claim 11 further includes: Before forming the semiconductor stack structure, a tunneling dielectric layer is formed on the substrate; A fourth dielectric liner is formed in the substrate adjacent to the semiconductor stack structure, wherein the fourth dielectric liner surrounds the first dielectric fill layer and is adjacent to a plurality of third sides of the tunneling dielectric layer and a plurality of first sides of the first floating gate, wherein the fourth dielectric liner is formed of the first material.

Images