Semiconductor devices and manufacturing methods thereof

TW202634926APending Publication Date: 2026-08-16KIOXIA CORP
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Patent Information

Application Number
TW114129197
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-04-15
Filing Date
2025-07-31
Publication Date
2026-08-16

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    Figure TWG2TA001072538_002
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    Figure TWG2TA001072538_003
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Abstract

This invention provides a semiconductor device and a method for manufacturing the same, which can suppress parasitic capacitance between wirings to a low level. The semiconductor device of this embodiment includes a multilayer. The multilayer includes a plurality of conductive layers and a plurality of insulating layers alternately stacked in a first direction. A first insulating film is disposed relative to the multilayer in the first direction. A third wiring includes a plurality of first wirings and a plurality of second wirings. The third wiring is disposed relative to the first insulating film in the first direction, extends in a second direction intersecting the first direction, and is arranged in a third direction intersecting both the first and second directions. A fifth wiring is disposed relative to any one of the plurality of first wirings, i.e., a fourth wiring, in the first direction. A first contact electrically connects the fourth wiring and the fifth wiring. A second insulating film is disposed between a sixth wiring and the fourth wiring, wherein the sixth wiring is any other one of the plurality of first wirings and is adjacent to the fourth wiring. The third insulating film is disposed in a first direction relative to the first insulating film, and an air gap is formed between two adjacent second wirings in the plurality of second wirings. The first contact and the second insulating film are disposed in a first region when viewed from the first direction. The third insulating film is disposed in a second region different from the first region when viewed from the first direction.
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