Memory device and fabrication method thereof

Abstract

A memory device and the fabrication method thereof are provided by embodiments of the present disclosure. The method includes forming an epitaxy layer on a first substrate region while exposing a second substrate region, forming a high-k dielectric layer on the epitaxy layer and the second substrate region, forming a first sacrificial layer on the high-k dielectric layer above the first substrate region while exposing the high-k dielectric layer above the second substrate region, forming a metal layer on the first sacrificial layer and the high-k dielectric layer, performing an annealing process to form a doping region in the high-k dielectric layer above the second substrate region, forming a gate electrode layer and a gate capping layer on the high-k dielectric layer, and patterning the gate capping layer, the gate electrode layer, and the high-k dielectric layer into gate structures above the epitaxy layer and above the doping region.

Description

Technical Field

[0001] This disclosure relates to memory devices and methods of manufacturing them. Prior Technology

[0002] As semiconductor technology advances, the critical dimension (CD) of semiconductor components in memory devices decreases, thus increasing the component integration density within memory devices. However, with the reduction in critical dimension, semiconductor manufacturing processes also face many challenges. For example, the reduction in the size of semiconductor components in memory devices may lead to more frequent leakage currents associated with the gate of the memory device. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method of manufacturing a memory device includes the following steps: Forming a shallow trench isolation region in a substrate to divide the substrate into a first substrate region and a second substrate region. Forming an epitaxial layer on the first substrate region and exposing the second substrate region. Forming a high-k dielectric layer on the epitaxial layer and the second substrate region. Forming a first sacrificial layer on a first portion of the high-k dielectric layer above the first substrate region and exposing a second portion of the high-k dielectric layer above the second substrate region. Forming a metal layer on the first sacrificial layer and the high-k dielectric layer. Performing an annealing process to form a doped region in the high-k dielectric layer above the second substrate region. Removing the metal layer and the first sacrificial layer. Forming a gate electrode layer on the high-k dielectric layer and forming a gate capping layer on the gate electrode layer. Patterning the gate capping layer, the gate electrode layer, and the high-k dielectric layer into a first gate structure above the epitaxial layer and a second gate structure above the doped region.

[0004] In some embodiments, the method further includes forming a second sacrificial layer covering the metal layer, forming a capping layer covering the second sacrificial layer, performing an annealing process to drive metal elements of the metal layer into a high dielectric constant dielectric layer to form a doped region, and removing the capping layer and the second sacrificial layer after the annealing process.

[0005] In some embodiments, the first sacrificial layer and the second sacrificial layer are formed of the same material.

[0006] In some embodiments, after the annealing process, the metal elements of the metal layer stop at the bottom of the high dielectric constant dielectric layer.

[0007] In some embodiments, after forming a first sacrificial layer over a first substrate region, a plurality of sidewalls of the first sacrificial layer are flush with a plurality of sidewalls of the epitaxial layer.

[0008] In some embodiments, the sidewalls of the doped region are flush with the sidewalls of the first sacrificial layer.

[0009] In some embodiments, forming an epitaxial layer on a first substrate region includes epitaxially growing a silicon-containing layer using a SiH4-based precursor on the first substrate region, and forming an epitaxial layer using a germanium-doped silicon-containing layer.

[0010] In some embodiments, a high dielectric constant dielectric layer covers the top surface of the epitaxial layer, the sidewalls of the epitaxial layer, and the top surface of the second substrate region, and the high dielectric constant dielectric layer has a flat top surface.

[0011] In some embodiments, after an epitaxial layer is formed on the first substrate region, the epitaxial layer extends to the top surface of the shallow trench isolation region.

[0012] In some embodiments, an etching process is used to remove the metal layer and the first sacrificial layer, with the etching process stopping at the top surface of the high dielectric constant dielectric layer.

[0013] In some embodiments, the method further includes patterning an epitaxial layer such that a plurality of sidewalls of the epitaxial layer are flush with a plurality of sidewalls of a first gate structure, and patterning a doped region such that a plurality of sidewalls of the doped region are flush with a plurality of sidewalls of a second gate structure.

[0014] In some embodiments, after the annealing process, the doped region is located between the bottom surface of the high dielectric constant layer above the second substrate region and the middle position of the high dielectric constant layer.

[0015] According to some embodiments of this disclosure, a memory device includes a first transistor having a first conductivity type and a second transistor having a second conductivity type different from the first conductivity type. The first transistor includes a first substrate region, an epitaxial layer above the first substrate region, and a first high-dielectric-constant metal gate structure on the epitaxial layer. The second transistor includes a second substrate region, a doped region above the second substrate region, and a second high-dielectric-constant metal gate structure on the doped region. The doped region includes a high-dielectric-constant dielectric material doped with a metal element. The first high-dielectric-constant metal gate structure includes a high-dielectric-constant dielectric layer having a high-dielectric-constant dielectric material, a gate electrode layer on the high-dielectric-constant dielectric layer, and a gate capping layer on the gate electrode layer.

[0016] In some embodiments, the concentration of the metal element increases from the bottom surface of the doped region toward the top surface of the doped region.

[0017] In some embodiments, the highest concentration of the metal element in the doped region is located on the top surface of the doped region.

[0018] In some embodiments, the thickness of the doped region is the same as the thickness of the epitaxial layer.

[0019] In some embodiments, the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0020] In some embodiments, the epitaxial layer is a SiGe layer, and the doped region is a high dielectric constant dielectric material doped with lanthanum.

[0021] In some embodiments, the first high dielectric constant metal gate structure is separated from the second high dielectric constant metal gate structure, the epitaxial layer is separated from the doped region, and the shallow trench isolation region is inserted between the first substrate region and the second substrate region.

[0022] In some embodiments, the epitaxial layer serves as a channel region between the first high dielectric constant metal gate structure and the first substrate region.

[0023] According to the above embodiments, a method of manufacturing a memory device includes forming a first sacrificial layer for a first transistor before forming a high-dielectric-constant metal gate structure to prevent metal elements in a second transistor from diffusing into the channel region of the first transistor. Therefore, the epitaxial layer in the first transistor and the doped region in the second transistor can reduce the threshold voltage for operating the memory device, and the high-dielectric-constant metal gate structure reduces leakage current in the memory device. Simple Explanation of the Diagram

[0024] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a flowchart of an example method for manufacturing a memory device according to some embodiments of the present disclosure. Figures 2 through 9 illustrate schematic cross-sectional views of the memory device at various manufacturing stages according to some embodiments of the present disclosure. Implementation

[0025] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0027] According to some embodiments of this disclosure, Figure 1 illustrates a flowchart of an example method 100 for manufacturing a memory device. The following description will be based on Figures 1 and 2 through 9, wherein Figures 2 through 9 illustrate schematic cross-sectional views of the memory device 200 at various manufacturing stages according to some embodiments of this disclosure. Method 100 is merely an example, and in other embodiments, additional steps may be added before, during, or after method 100, and some of the steps may be moved, replaced, or deleted. In other embodiments, additional features may be added to the illustrated memory device 200, and some of the features may be replaced, modified, or deleted.

[0028] In block 110, method 100 includes forming shallow trench isolation (STI) regions in a substrate to divide the substrate into a first substrate region and a second substrate region. Referring to Figure 2, in one embodiment of block 110, a substrate 210 for forming a memory device 200 is provided. In some embodiments, substrate 210 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 210 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 210 may include compound semiconductors and / or alloy semiconductors.

[0029] A shallow trench isolation region 220 is formed in substrate 210, wherein the shallow trench isolation region 220 extends from the top surface of substrate 210 toward the bottom surface of substrate 210. The bottom surface of the shallow trench isolation region 220 may terminate in substrate 210 as shown in Figure 2, or in some other embodiments the shallow trench isolation region 220 may extend through substrate 210. The shallow trench isolation region 220 divides substrate 210 into a first substrate region 212 and a second substrate region 214. In other words, the shallow trench isolation region 220 intersects between the first substrate region 212 and the second substrate region 214. The first substrate region 212 and the second substrate region 214 will serve as the substrate for two transistors of different conductivity types. For example, the first substrate region 212 may be the substrate of an n-type metal-oxide-semiconductor (NMOS) transistor of the memory device 200, while the second substrate region 214 may be the substrate of a p-type metal-oxide-semiconductor (PMOS) transistor of the memory device 200.

[0030] In some embodiments, the shallow trench isolation region 220 may be formed of an oxide, such as SiOx. Forming the shallow trench isolation region 220 may be achieved by etching trenches in the substrate 210 and filling the trenches with an oxide material. Although the shallow trench isolation region 220 in Figure 2 is depicted as a trapezoid with a larger top width on the top surface of the substrate 210 and a smaller bottom width below the top surface of the substrate 210, the shallow trench isolation region 220 may have other shapes in other embodiments. After forming the shallow trench isolation region 220, a planarization process, such as chemical mechanical polishing (CMP), may be performed on the substrate 210 and the shallow trench isolation region 220 before forming other components on the substrate 210.

[0031] In block 120, method 100 includes forming an epitaxial layer on a first substrate region and exposing a second substrate region. Referring to Figure 2, in one embodiment of block 120, an epitaxial layer 230 is formed on the first substrate region 212, but the epitaxial layer 230 is not formed on the second substrate region 214. Therefore, the epitaxial layer 230 covers the top surface of the first substrate region 212 while exposing the second substrate region 214. The epitaxial layer 230 may extend to the top surface of the shallow trench isolation region 220, or the sidewalls of the epitaxial layer 230 may be located on the top surface of the first substrate region 212. The epitaxial layer 230 may be used as a channel region between a subsequently formed high-k dielectric metal gate and the first substrate region 212, wherein the epitaxial layer 230 reduces the threshold voltage (Vt) of the first transistor operating the memory device 200.

[0032] In some embodiments where the first substrate region 212 is used for a p-type transistor, the epitaxial layer 230 can be formed of a crystalline semiconductor material, such as, but not limited to, SiGe. For example, a silicon-containing layer can be grown on the first substrate region 212 using an epitaxial or deposition process employing a SiH4-based gas as a precursor, such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), other suitable deposition processes, or combinations thereof. The epitaxial layer 230 is then formed by doping the silicon-containing region with germanium (Ge). During the deposition and / or doping of the epitaxial layer 230, a masking layer (not shown) can be used to cover the second substrate region 214. Because the epitaxial layer 230 is formed using a SiH4-based deposition process, the formed epitaxial layer 230 can have low surface roughness, reducing defects in the memory device 200.

[0033] In block 130, method 100 includes forming a high-dielectric-constant dielectric layer on the epitaxial layer and the second substrate region. Referring to Figure 3, in one embodiment of block 130, a high-dielectric-constant dielectric layer 240 is formed on the epitaxial layer 230 and the second substrate region 214. The thickness of the high-dielectric-constant dielectric layer 240 along the z-axis is sufficient to cover the top surface of the epitaxial layer 230, the sidewalls of the epitaxial layer 230 adjacent to the second substrate region 214, and the top surface of the second substrate region 214. After forming the high-dielectric-constant dielectric layer 240, a planarization process (e.g., chemical mechanical polishing) can be performed on the high-dielectric-constant dielectric layer 240 to provide a flat top surface of the high-dielectric-constant dielectric layer 240.

[0034] In some embodiments, the high-dielectric-constant dielectric layer 240 may be formed of a dielectric material having a dielectric constant (k-value) higher than that of SiO2, such as HfO2, HfSiOx, TiO2, ZrO2, other dielectric materials having a dielectric constant higher than 3.9, or combinations thereof. The high-dielectric-constant dielectric layer 240 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), or other suitable deposition processes.

[0035] In block 140, method 100 includes forming a first sacrificial layer on a high-dielectric-constant dielectric layer located above a first substrate region, and exposing a high-dielectric-constant dielectric layer located above a second substrate region. Referring to Figure 4, in one embodiment of block 140, a first sacrificial layer 250 is formed over the first substrate region 212, but the first sacrificial layer 250 is not formed over the second substrate region 214. Therefore, the first sacrificial layer 250 covers the top surface of a first portion of the high-dielectric-constant dielectric layer 240 located over the first substrate region 212, while the first sacrificial layer 250 exposes the top surface of a second portion of the high-dielectric-constant dielectric layer 240 located over the second substrate region 214. The first sacrificial layer 250 may extend to the top surface of the high-dielectric-constant dielectric layer 240 located over the shallow trench isolation region 220. Multiple sidewalls of the first sacrificial layer 250 may be flush with multiple sidewalls of the epitaxial layer 230.

[0036] In some embodiments, the first sacrificial layer 250 may be formed of a hard masking material, which can prevent metal elements from penetrating into the first sacrificial layer 250 in subsequent processes. For example, the first sacrificial layer 250 may be formed of a nitride, such as titanium nitride (TiN) or silicon nitride (SiN). The first sacrificial layer 250 may be formed by performing a deposition process using a hard masking material on the entire top surface of the high dielectric constant dielectric layer 240, and by removing a portion of the hard masking material located above the second substrate region 214 by a wet etching process.

[0037] In block 150, method 100 includes forming a metal layer on a first sacrificial layer and a high-dielectric-constant dielectric layer, forming a second sacrificial layer on the metal layer, and forming a capping layer on the second sacrificial layer. Referring to Figure 5, in one embodiment of block 150, a metal layer 260 is formed over a first substrate region 212 and a second substrate region 214. The thickness of the metal layer 260 along the z-axis is sufficient to cover the top surface of the first sacrificial layer 250, the sidewalls of the first sacrificial layer 250, and the top surface of the high-dielectric-constant dielectric layer 240 located over the second substrate region 214. In some embodiments, the metal layer 260 may be formed from a metal element that will serve as a second channel region over the second substrate region 214. For example, when the second substrate region 214 will be used as an n-type transistor, the metal layer 260 may be formed from lanthanum (La). The metal layer 260 may be conformally formed by atomic layer deposition, sputtering, electroplating, or a combination thereof.

[0038] A second sacrificial layer 270 is formed on the metal layer 260, wherein the second sacrificial layer 270 conformally covers the metal layer 260. Next, a capping layer 280 is formed on the second sacrificial layer 270, wherein the capping layer 280 conformally covers the second sacrificial layer 270. In some embodiments, the second sacrificial layer 270 may be formed of the same material as the first sacrificial layer 250, such that the first sacrificial layer 250 and the second sacrificial layer 270 can prevent metal elements in the metal layer 260 from penetrating into the first sacrificial layer 250 and the second sacrificial layer 270 in subsequent processes. For example, both the first sacrificial layer 250 and the second sacrificial layer 270 may be formed of a TiN layer with a thickness ranging from 1 nm to 5 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. The capping layer 280 may be formed of amorphous silicon. The formation of the second sacrificial layer 270 and the capping layer 280 may be achieved by a highly conformal deposition process, such as atomic layer deposition.

[0039] In block 160, method 100 includes performing an annealing process to form a doped region in a high-k dielectric layer located above the second substrate region. Referring to Figure 6, in one embodiment of block 160, an annealing process is performed on the structure in Figure 5. During the annealing process, metal elements in metal layer 260 are driven into a high-k dielectric layer 240 above the second substrate region 214. Thus, the metal elements in metal layer 260 dope a portion of the high-k dielectric layer 240 located above the second substrate region 214, thereby forming a doped region 290 in the high-k dielectric layer 240. The doped region 290 located between the subsequently formed high-k dielectric metal gate and the second substrate region 214 can reduce the threshold voltage of the second transistor operating the memory device 200.

[0040] Since the first sacrificial layer 250 covers the high-dielectric-constant dielectric layer 240 located above the first substrate region 212, metal elements in the metal layer 260 will not diffuse into the high-dielectric-constant dielectric layer 240 located above the first substrate region 212. In other words, during the formation of the doped region 290, the first sacrificial layer 250 protects the high-dielectric-constant dielectric layer 240 and the epitaxial layer 230 located above the first substrate region 212. This ensures that the transistor including the epitaxial layer 230 has a highly stable epitaxial layer 230 and a threshold voltage. In addition, the second sacrificial layer 270 located on the metal layer 260 can prevent metal elements from diffusing into the capping layer 280.

[0041] In some embodiments, an annealing process can be controlled to form a doped region 290 at the bottom of the high-k dielectric layer 240. For example, an annealing process can be performed at a temperature of about 950°C to about 1020°C for a duration of about 1 second to 5 seconds, causing the metal elements diffusing from the metal layer 260 to stop at the bottom surface of the high-k dielectric layer 240. After the annealing process, the doped region 290 can be formed between the bottom surface of the high-k dielectric layer 240 and a plane below the midpoint of the high-k dielectric layer 240, or the doped region 290 can be formed between the bottom surface of the high-k dielectric layer 240 and a plane flush with the midpoint of the high-k dielectric layer 240. The thickness of the doped region 290 along the z-axis can be similar to or the same as the thickness of the epitaxial layer 230. For example, the thickness of the doped region 290 can be in the range of 0.5 nm to 1.5 nm, such as 0.5 nm, 1 nm, or 1.5 nm. The sidewall of the doped region 290 relative to the first substrate region 212 can be flush with the sidewall of the first sacrificial layer 250, or the sidewall of the doped region 290 can directly contact the sidewall of the epitaxial layer 230. The concentration of metal elements from the metal layer 260 can increase from the bottom surface of the doped region 290 toward the top surface of the doped region 290. For example, the highest lanthanum concentration in the doped region 290 can be located at the top surface of the doped region 290, while the lowest lanthanum concentration located at the bottom surface of the doped region 290 can be close to zero.

[0042] In block 170, method 100 includes removing a material layer located above the high-k dielectric layer. Referring to Figure 7, in one embodiment of block 170, an etching process is performed on the structure in Figure 6 to remove the capping layer 280, the second sacrificial layer 270, the metal layer 260, and the first sacrificial layer 250. The etching process can be a multi-step wet etching process or a dry etching process, wherein the etching process stops at the top surface of the high-k dielectric layer 240, so that during the etching process of block 170, the high-k dielectric layer 240, the doped region 290 in the high-k dielectric layer 240, and the epitaxial layer 230 remain substantially unetched.

[0043] In block 180, method 100 includes forming a gate electrode layer on a high-dielectric-constant dielectric layer and forming a gate capping layer on the gate electrode layer. Referring to Figure 8, in one embodiment of block 180, a gate electrode layer 300 is formed on a high-dielectric-constant dielectric layer 240 to cover the top surface of the high-dielectric-constant dielectric layer 240. Next, a gate capping layer 310 is formed on the gate electrode layer 300. In some embodiments, the gate electrode layer 300 may be formed of a metal, a metal nitride, other conductive materials, or a combination thereof, and the gate electrode layer 300 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition processes. The gate capping layer 310 may be formed of a conductive or non-conductive material different from the gate electrode layer 300, and the gate capping layer 310 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes. For example, the gate electrode layer 300 can be formed of TiN, while the gate capping layer can be formed of polycrystalline silicon. After the gate capping layer 310 is formed, a planarization process (e.g., chemical mechanical polishing) can be performed on the gate capping layer 310 to provide a flat top surface for the gate stack.

[0044] In block 190, method 100 includes patterning a gate capping layer, a gate electrode layer, and a high-dielectric-constant dielectric layer into a first gate structure located above a first substrate region and a second gate structure located above a second substrate region. Referring to Figure 9, in one embodiment of block 190, the gate capping layer 310, the gate electrode layer 300, and the high-dielectric-constant dielectric layer 240 located above the first substrate region 212 are patterned into a first gate structure 322. The epitaxial layer 230 below the first gate structure 322 may also be patterned such that multiple sidewalls of the epitaxial layer 230 are flush with multiple sidewalls of the first gate structure 322. Similarly, the gate capping layer 310, the gate electrode layer 300, and the high-dielectric-constant dielectric layer 240 located above the second substrate region 214 are patterned into a second gate structure 324. The doped region 290 in the high dielectric constant dielectric layer 240 can also be patterned so that multiple sidewalls of the doped region 290 are flush with multiple sidewalls of the second gate structure 324.

[0045] After forming the first gate structure 322 and the second gate structure 324, the memory device 200 includes a first transistor 202 and a second transistor 204 separated by a shallow trench isolation region 220. The first transistor 202 has a first conductivity type, and the second transistor 204 has a second conductivity type different from the first conductivity type. The first transistor 202 includes a first substrate region 212, an epitaxial layer 230 located above the first substrate region 212, and a first gate structure 322 located on the epitaxial layer 230. The second transistor 204 includes a second substrate region 214, a doped region 290 located above the second substrate region 214, and a second gate structure 324 located on the doped region 290. The first gate structure 322 and the second gate structure 324 are high-dielectric-constant metal gate structures including a high-dielectric-constant dielectric layer 240, a gate electrode layer 300, and a gate capping layer 310.

[0046] In some embodiments where the first transistor 202 is a p-type transistor and the second transistor 204 is an n-type transistor, a high-dielectric-constant metal gate structure within either the first transistor 202 or the second transistor 204 can reduce leakage current associated with the high-dielectric-constant metal gate structure, such as leakage current between the high-dielectric-constant metal gate structure and the source / drain regions. Compared to a transistor having a high-dielectric-constant metal gate structure directly located on the substrate, the epitaxial layer 230 located between the first gate structure 322 and the first substrate region 212 can reduce the threshold voltage for operating the first transistor 202. Similarly, a lanthanum-doped region 290 located between the second gate structure 324 and the second substrate region 214 can reduce the threshold voltage for operating the second transistor 204. Furthermore, the epitaxial layer 230 formed using a SiH4 precursor can reduce the surface roughness of the epitaxial layer 230 and corresponding defects in the memory device 200.

[0047] According to the above embodiments, the method for manufacturing a memory device disclosed herein includes forming a first sacrificial layer above a channel region of a first transistor to prevent the diffusion of metal elements from a second transistor into the channel region of the first transistor. Therefore, the epitaxial layer in the first transistor and the metal-doped region in the second transistor can be stable and reduce the threshold voltage of the transistor operating the memory device. The manufacturing method also includes forming a high-dielectric-constant metal gate structure above the epitaxial layer and the doped region, thereby reducing leakage current in the transistor without causing the threshold voltage of the operating transistor to deviate from a value far from 0 volts.

[0048] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0049] 100: Method 110, 120, 130, 140, 150, 160, 170, 180, 190: Square 200: Memory device 202: First Transistor 204: Second transistor 210:Substrate 212: First substrate region 214: Second substrate region 220: Shallow trench isolation area 230: Epitaxial layer 240: High dielectric constant dielectric layer 250: First Sacrifice Layer 260: Metal layer 270: Second Sacrificial Layer 280: Covering layer 290: Doped region 300: Gate electrode layer 310: Gate capping layer 322: First gate structure 324: Second gate structure x, y, z: axes

[0050] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a memory device, comprising: A shallow trench isolation region is formed in a substrate to divide the substrate into a first substrate region and a second substrate region. An epitaxial layer is formed on the first substrate region, exposing the second substrate region; a high-dielectric-constant dielectric layer is formed on the epitaxial layer and the second substrate region; a first sacrificial layer is formed on a first portion of the high-dielectric-constant dielectric layer located above the first substrate region, exposing a second portion of the high-dielectric-constant dielectric layer located above the second substrate region; a metal layer is formed on the first sacrificial layer and the high-dielectric-constant dielectric layer; an annealing process is performed to form a doped region in the high-dielectric-constant dielectric layer located above the second substrate region; Remove the metal layer and the first sacrificial layer; form a gate electrode layer on the high dielectric constant layer and a gate capping layer on the gate electrode layer; and pattern the gate capping layer, the gate electrode layer and the high dielectric constant layer into a first gate structure located above the epitaxial layer and a second gate structure located above the doped region.

2. The method as described in claim 1, further comprising: A second sacrificial layer is formed to cover the metal layer; A covering layer is formed over the second sacrificial layer; The annealing process is performed to drive a metal element of the metal layer into the high dielectric constant dielectric layer to form the doped region; and after the annealing process, the capping layer and the second sacrificial layer are removed.

3. The method as described in claim 2, wherein the first sacrificial layer and the second sacrificial layer are formed of the same material.

4. The method as described in claim 2, wherein after the annealing process, the metal element of the metal layer stops at the bottom of the high dielectric constant dielectric layer.

5. The method as described in claim 1, wherein after forming the first sacrificial layer over the first substrate region, a plurality of sidewalls of the first sacrificial layer are flush with a plurality of sidewalls of the epitaxial layer.

6. The method as described in claim 1, wherein one sidewall of the doped region is flush with one sidewall of the first sacrificial layer.

7. The method as described in claim 1, wherein forming the epitaxial layer on the first substrate region comprises: A silicon-containing layer is epitaxially grown on the first substrate region using a SiH4-based precursor. The epitaxial layer is formed by doping the silicon-containing layer with germanium.

8. The method as claimed in claim 1, wherein the high dielectric constant dielectric layer covers a top surface of the epitaxial layer, a sidewall of the epitaxial layer, and a top surface of the second substrate region, and the high dielectric constant dielectric layer has a flat top surface.

9. The method as claimed in claim 1, wherein after the epitaxial layer is formed on the first substrate region, the epitaxial layer extends to a top surface of the shallow trench isolation region.

10. The method as described in claim 1, wherein an etching process is used to remove the metal layer and the first sacrificial layer, the etching process stopping at a top surface of the high dielectric constant dielectric layer.

11. The method as described in claim 1, further comprising: The epitaxial layer is patterned so that multiple sidewalls of the epitaxial layer are flush with multiple sidewalls of the first gate structure; The doped region is patterned such that multiple sidewalls of the doped region are flush with multiple sidewalls of the second gate structure.

12. The method as claimed in claim 1, wherein after the annealing process, the doped region is located between a bottom surface of the high dielectric constant layer above the second substrate region and an intermediate position of the high dielectric constant layer.

13. A memory device, comprising: A first transistor having a first conductivity type includes: a first substrate region; an epitaxial layer located above the first substrate region; and a first high-dielectric-constant metal gate structure located on the epitaxial layer; and a second transistor having a second conductivity type, wherein the second conductivity type is different from the first conductivity type, the second transistor including: a second substrate region; a doped region directly formed on an upper surface of the second substrate region, wherein the doped region includes a high-dielectric-constant dielectric material doped with a metal element; and a second high-dielectric-constant metal gate structure located on the doped region, wherein the first high-dielectric-constant metal gate structure includes a high-dielectric-constant dielectric layer having the high-dielectric-constant dielectric material, a gate electrode layer located on the high-dielectric-constant dielectric layer, and a gate capping layer located on the gate electrode layer.

14. The memory device as claimed in claim 13, wherein the concentration of the metal element increases from a bottom surface of the doped region toward a top surface of the doped region.

15. The memory device as claimed in claim 13, wherein the highest concentration of the metal element in the doped region is located on a top surface of the doped region.

16. The memory device as claimed in claim 13, wherein the thickness of the doped region is the same as the thickness of the epitaxial layer.

17. The memory device as claimed in claim 13, wherein the first transistor is a p-type transistor and the second transistor is an n-type transistor.

18. The memory device as claimed in claim 13, wherein the epitaxial layer is a SiGe layer and the doped region is the high-dielectric-constant dielectric material doped with lanthanum.

19. The memory device as claimed in claim 13, wherein the first high-dielectric-constant metal gate structure is separated from the second high-dielectric-constant metal gate structure, the epitaxial layer is separated from the doped region, and a shallow trench isolation region is interposed between the first substrate region and the second substrate region.

20. The memory device as claimed in claim 13, wherein the epitaxial layer serves as a channel region between the first high-dielectric-constant metal gate structure and the first substrate region.

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