Method for forming semiconductor structure
Patent Information
- Application Number
- TW114104468
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-07
- Publication Date
- 2026-08-16
- Estimated Expiration
- 2045-02-06
AI Technical Summary
Existing flash memory manufacturing methods struggle to maintain high yield rates and improve performance as devices miniaturize, particularly in ensuring effective isolation between bit lines to prevent leakage current.
A method involving the formation of trenches in a substrate, followed by the creation of air gaps in a dielectric layer within these trenches, which are expanded through etching and ion implantation to form an etch stop layer, and finally sealed with additional dielectric layers to create an isolation structure with air gaps, enhancing insulation between bit line structures.
The method improves insulation between bit lines, maintaining yield and performance of flash memory devices by effectively preventing leakage current, thus supporting the miniaturization efforts in semiconductor structures.
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for forming a semiconductor structure, and particularly to a method for forming a flash memory structure. [Previous Technology]
[0002] Flash memory is a type of non-volatile memory with high capacity, high read / write speed, low power consumption, and low cost. Due to its non-volatile nature, data can still be stored in flash memory after power is turned off, therefore, flash memory is widely used.
[0003] To increase the component density within flash memory devices and improve their overall performance, current flash memory device manufacturing technologies continue to strive towards miniaturization of component size. For example, with device miniaturization, better isolation between bit line structures is required to meet device performance requirements, such as reducing the possibility of leakage current. Therefore, the industry still needs to improve flash memory device manufacturing methods to maintain the yield rate of memory devices. [Summary of the Invention]
[0004] Embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; sequentially forming a first gate layer and a masking layer above the substrate; etching the substrate to form a plurality of active regions, wherein the active regions are isolated from each other by a plurality of trenches, and the trenches penetrate the masking layer and the first gate layer; forming a first dielectric layer in the trenches, the first dielectric layer having a first air gap; etching back the first dielectric layer to expose the top of the first air gap; performing an ion implantation process on the first dielectric layer to form an etch stop layer on the upper part of the first dielectric layer and surrounding the top of the first air gap; removing the portion of the first dielectric layer exposed by the first air gap to form a second air gap; forming a second dielectric layer on the first dielectric layer in the trench; etching back the second dielectric layer and the masking layer to expose the top surface of the first gate layer, and the second dielectric layer remaining on the top of the first air gap; compliantly forming an inter-gate dielectric layer on the substrate and the first gate layer; and forming a second gate layer on the inter-gate dielectric layer.
Implementation Method
[0005] The following description provides detailed examples in conjunction with the accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same elements will be designated with the same symbols in the following description.
[0006] Figures 1 to 9 are schematic cross-sectional views of each process stage of the method for forming a semiconductor structure 10 according to an embodiment of the present invention. Referring to Figure 1, a substrate 100 is provided. In one embodiment, the substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; a compound semiconductor substrate, such as a silicon carbide, gallium arsenide, indium arsenide, or indium phosphide substrate; or an alloy semiconductor substrate, such as SiGe, SiGeC, GaAsP, or GaInP. In other embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate. The aforementioned semiconductor-on-insulator substrate may include a substrate, a buried oxide layer disposed on the substrate, and a semiconductor layer disposed on the buried oxide layer.
[0007] Referring again to Figure 1, a gate layer 110 and a masking layer 120 are sequentially formed above the substrate 100. The gate layer 110 can subsequently serve as a floating gate of the semiconductor structure 10. The masking layer 120 can be used to define the subsequently formed active region and trench. In one embodiment, a substrate 105 can be formed on the substrate 100 before forming the gate layer 110. The substrate 105 can serve as a tunneling oxide layer of the semiconductor structure 10. In one embodiment, the substrate 105 can comprise an oxide, such as silicon oxide, and can be formed by a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. In one embodiment, the gate layer 110 can comprise doped polysilicon, undoped polysilicon, a metal, a polycide, or a combination thereof, and can be formed by a deposition process such as chemical vapor deposition, other suitable processes, or a combination thereof. In one embodiment, the masking layer 120 may comprise a nitride, such as silicon nitride, and may be formed by a process such as chemical vapor deposition or other suitable process.
[0008] Referring again to Figure 1. After forming the substrate 105, gate layer 110, and mask layer 120, the substrate 100 is etched to form a plurality of active regions 130. The active regions 130 are isolated from each other by a plurality of trenches 140, and the trenches 140 penetrate the mask layer 120 and the gate layer 110. In other words, the trenches 140 define the location of the active regions 130. More specifically, the etching process of the substrate 100 may include first forming a patterned photoresist layer (not shown) to define the location of the active regions 130, then performing an etching process to form the trenches 140, and then removing the patterned photoresist layer to expose the top surface of the mask layer 120. In one embodiment, the trenches 140 may be formed by an anisotropic etching process (or a directional etching process), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or a combination thereof. In one embodiment, after the trench 140 is formed, the patterned photoresist layer can be removed by means of processes such as etching, stripping, ashing, or a combination thereof.
[0009] Next, referring to Figure 2, a dielectric layer 150 is formed in the trench 140, and the dielectric layer 150 has a first air gap 152. In one embodiment, before forming the dielectric layer 150, a liner 145 may be formed to cover the trench 140, and the liner 145 may assist in the formation of the dielectric layer 150. In one embodiment, after forming the dielectric layer 150, a chemical mechanical polishing process may be performed to expose the top surface of the mask layer 120. In one embodiment, the material of the dielectric layer 150 may comprise oxides or nitrides, such as tetraethylorthosilicate (TEOS), and may be formed by processes such as non-compliant chemical vapor deposition, high aspect ratio processes, or other suitable processes. It should be noted that, in this embodiment of the invention, since the dielectric layer 150 is formed using a process with a faster deposition rate and poorer filling capacity, the opening of the trench 140 is sealed and a first air gap 152 is formed before the trench 140 is completely filled. The first air gap 152 will be further expanded into a second air gap 200 in subsequent processes, thereby providing better insulation between bit line structures.
[0010] Referring to Figure 3, after forming the dielectric layer 150 and the first air gap 152, an etch-back process 160 is performed on the dielectric layer 150 to expose the top 152t of the first air gap 152. In one embodiment, the etch-back process 160 etches the top surface of the dielectric layer 150 below the top surface of the gate layer 110, and the etch-back process 160 etches the top surface of the dielectric layer 150 above the top surface of the active region 130. The depth of the dielectric layer 150 removed by the etch-back process 160 depends on design requirements. In one embodiment, the etch-back process 160 may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or combinations thereof.
[0011] Referring then to Figure 4, after performing the etch-back process 160, an ion implantation process 170 is performed on the dielectric layer 150 to form an etch stop layer 180 on the upper portion 150t of the dielectric layer 150. As shown in Figure 4, the etch stop layer 180 surrounds the top 152t of the first air gap 152 and exposes the top 152t of the first air gap 152. In one embodiment, the bottom surface of the etch stop layer 180 is higher than the top surface of the substrate 105. In one embodiment, the elements used in the ion implantation process 170 may include C, N, Si, or other suitable elements.
[0012] Referring to Figures 5 and 6, after forming the etch stop layer 180, an etching process 190 is performed to remove a portion of the dielectric layer 150 exposed in the first air gap 152 to form the second air gap 200. In one embodiment, the etching process 190 may include a wet etching process. In one example, the etchant of the etching process 190 (e.g., a wet etching process) can flow into the first air gap 152 through the top 152t of the first air gap 152 to remove a portion of the dielectric layer 150. More specifically, the etching process 190 is an isotropic etching process, in which the etchant of the etching process 190 flows into the first air gap 152 and etches the dielectric layer 150 located on the sidewalls and bottom of the first air gap 152. It is worth noting that the etching process 190 does not completely etch the dielectric layer 150, that is, the second air gap 200 formed by the etching process 190 does not directly contact the active region 130. In one embodiment, the etching process 190 may select an etchant that selectively etches only the material of the dielectric layer 150, while the gate layer 110, the mask layer 120, and the etch stop layer 180 are not substantially etched.
[0013] Referring again to Figure 6, the projected area of the second air gap 200 on the substrate 100 is larger than the projected area of the first air gap 152 on the substrate 100. In other words, since the second air gap 200 is formed by etching the first air gap 152, the second air gap 200 is larger than the first air gap 152. In one embodiment, the width 202 of the second air gap 200 is larger than the width 154 of the first air gap 152. In one embodiment, the width 202 of the second air gap 200 is smaller than the width 142 of each trench 140. In one embodiment, the depth 204 of the second air gap 200 is larger than the depth 156 of the first air gap 152. In one embodiment, the top surface of the second air gap 200 is higher than the top surface of the active region 130.
[0014] Referring then to Figure 7, after the second air gap 200 is formed, a dielectric layer 210 can be formed on the dielectric layer 150 in the trench 140. In one embodiment, the dielectric layer 210 only fills the top 152t of the first air gap 152, and does not fill the second air gap 200. In other words, the dielectric layer 210 is used to seal the top opening of the second air gap 200 (i.e., the top 152t of the first air gap 152). It is worth noting that in this embodiment of the invention, since the etch stop layer 180 is modified through the ion implantation process, it can have an etch selectivity ratio with the dielectric layer 150 in the etch process 190, so that the etch stop layer 180 is not actually etched. Consequently, the size of the top 152t of the first air gap 152 exposed by the etch stop layer 180 is not enlarged, which is beneficial for the dielectric layer 210 to seal the top opening of the second air gap 200. In one embodiment, the dielectric layer 210 is deposited using a faster deposition process to prevent the dielectric layer 210 from forming into and filling the second air gap 200. In one embodiment, after forming the dielectric layer 210, a chemical mechanical polishing process can be performed to expose the top surface of the mask layer 120. In one embodiment, the material of the dielectric layer 210 may comprise oxides or nitrides, such as tetraethoxysilane, and can be formed by deposition processes such as chemical vapor deposition, high aspect ratio processes, other suitable processes, or combinations thereof.
[0015] Referring to Figure 8, after the dielectric layer 210 is formed (i.e., after sealing the opening of the second air gap 200), an etch-back process 220 is performed on the dielectric layer 210 and the masking layer 120 to expose the top surface of the gate layer 110, while the dielectric layer 210 remains on the top 152t of the first air gap 152. In one embodiment, after performing the etch-back process 220, the dielectric layer 150, the etch stop layer 180, the second air gap 200, and the dielectric layer 210 together form an isolation structure, such as a shallow trench isolation structure. The aforementioned isolation structure incorporating air gaps can effectively improve leakage problems that may occur between bit line structures due to miniaturization. In one embodiment, the etch-back process 220 may include anisotropic etching processes (or directional etching processes), such as reactive ion etching, plasma etching, inductively coupled plasma etching, or dry etching combining the above.
[0016] Referring to Figure 9, after performing the etch-back process 220, an inter-gate dielectric layer 230 is compliantly formed on the substrate 100 and the gate layer 110, and a gate layer 240 is formed on the inter-gate dielectric layer 230. More specifically, the inter-gate dielectric layer 230 compliantly covers the sidewalls and top surface of the gate layer 110, and covers the top surface of the etch stop layer 180 and the dielectric layer 210. In one embodiment, the inter-gate dielectric layer 230 is in direct contact with the top surface of the etch stop layer 180, that is, the dielectric layer 210 does not remain on the etch stop layer 180. The gate layer 240 can subsequently serve as the control gate of the semiconductor structure 10. In one embodiment, the second air gap 200 is separated from the inter-gate dielectric layer 230 by the etch stop layer 180 and the dielectric layer 210. In one embodiment, the method for forming the inter-gate dielectric layer 230 may include a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof. In one embodiment, the inter-gate dielectric layer 230 comprises a composite layer composed of oxide / nitride / oxide (ONO), but the invention is not limited thereto; the inter-gate dielectric layer 230 may also be a single layer or other numbers of composite layers. In one embodiment, the material of the gate layer 240 may comprise doped polycrystalline silicon, undoped polycrystalline silicon, metal, polycrystalline metal silicide, or a combination thereof, and may be formed by a process such as chemical vapor deposition or other suitable processes.
[0017] After the inter-gate dielectric layer 230 and the gate layer 240 are formed, the gate layer 110, the inter-gate dielectric layer 230, and the gate layer 240 can jointly form a word line structure. After the word line structure is formed, other related components of the memory device can be formed, which will not be described further here.
[0018] In summary, the embodiments of the present invention provide a method for forming a semiconductor structure. First, a trench is formed in a substrate, and a dielectric layer with an air gap is formed in the trench. Then, the dielectric layer is etched back to expose the top of the air gap. Next, the dielectric layer surrounding the top of the air gap is modified by an ion implantation process to form an etch stop layer on top of the dielectric layer. The unmodified dielectric layer is further removed by an etching process to expand the air gap in the dielectric layer. An additional dielectric layer is used to seal the air gap, thereby obtaining an isolation structure containing an air gap that can block the bit line structure, thereby maintaining the yield and performance of the memory device.
[0019] Although the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of this invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]
[0020] Figures 1 to 9 are schematic cross-sectional views of each process stage of the semiconductor structure formation method according to embodiments of the present invention.
Claims
1. A method for forming a semiconductor structure, comprising: Provide a substrate; A first gate layer and a masking layer are sequentially formed above the substrate; the substrate is etched to form a plurality of active regions, wherein the active regions are isolated from each other by a plurality of trenches, and the trenches penetrate the masking layer and the first gate layer; a first dielectric layer is formed in the trenches, the first dielectric layer having a first air gap; the first dielectric layer is etched back to expose the top of the first air gap; an ion implantation process is performed on the first dielectric layer to form an etch stop layer on the upper part of the first dielectric layer and surrounding the top of the first air gap; the portion of the first dielectric layer exposed by the first air gap is removed to form a second air gap; a second dielectric layer is formed on the first dielectric layer in the trenches; the second dielectric layer and the masking layer are etched back to expose the top surface of the first gate layer, and the second dielectric layer remains on the top of the first air gap; An inter-gate dielectric layer is compliantly formed on the substrate and the first gate layer; and a second gate layer is formed on the inter-gate dielectric layer.
2. The method for forming a semiconductor structure as described in claim 1, further comprising, before forming the first gate layer: A liner is formed on the substrate, wherein the bottom surface of the etch stop layer is higher than the top surface of the liner.
3. The method for forming a semiconductor structure as described in claim 1, wherein the projected area of the second air gap on the substrate is greater than the projected area of the first air gap on the substrate.
4. The method of forming a semiconductor structure as claimed in claim 1, wherein the second air gap is separated from the gate dielectric layer by the etch stop layer and the second dielectric layer.
5. A method for forming a semiconductor structure as described in claim 1, wherein the step of removing a portion of the first dielectric layer exposed by the first air gap to form the second air gap includes: A wet etching process is used to etch a portion of the first dielectric layer exposed by the first air gap, wherein an etchant in the wet etching process flows into the first air gap through the top of the first air gap to remove a portion of the first dielectric layer.
6. A method for forming a semiconductor structure as described in claim 1, wherein the elements used in the ion implantation process include C, N, or Si.
7. A method for forming a semiconductor structure as described in claim 1, wherein the second dielectric layer fills only the top of the first air gap.
8. A method for forming a semiconductor structure as described in claim 1, wherein the step of etching back the first dielectric layer comprises: The first dielectric layer is etched back so that the top surface of the first dielectric layer is lower than the top surface of the first gate layer, and the top surface of the first dielectric layer is higher than the top surface of the active regions.
9. A method for forming a semiconductor structure as claimed in claim 1, wherein the intergate dielectric layer is in direct contact with the top surface of the etch stop layer.
10. A method for forming a semiconductor structure as claimed in claim 1, wherein the materials of the first gate layer and the second gate layer comprise polysilicon.
11. A method for forming a semiconductor structure as claimed in claim 1, wherein the intergate dielectric layer comprises an oxide / nitride / oxide (ONO) composite layer.
12. A method of forming a semiconductor structure as claimed in claim 1, wherein the top surface of the second air gap is higher than the top surface of the active regions.
13. A method for forming a semiconductor structure as claimed in claim 1, wherein the first dielectric layer and the second dielectric layer comprise oxides or nitrides.
14. The method of forming a semiconductor structure as claimed in claim 1, wherein the first dielectric layer, the etch stop layer, the second air gap, and the second dielectric layer together form a trench isolation structure.