Semiconductor memory devices

Abstract

One embodiment provides a semiconductor memory device that can shorten the step length. An embodiment of a semiconductor memory device includes: a stacked body consisting of a plurality of conductive layers WL stacked separately, having a stepped portion SP formed by processing the plurality of conductive layers WL into a stepped shape and including a plurality of stepped surfaces T that do not overlap with the upper conductive layers WL; pillars extending in the stacking direction of the stacked body LM within the stacked body offset from the stepped portion SP, forming memory cells MC at intersections with at least a portion of the plurality of conductive layers WL; and a plurality of contacts CC, which are disposed in the stepped portion SP and connected to the plurality of conductive layers WL respectively; and the plurality of contacts CC includes a first contact CC group, wherein the first contact CC group is disposed in the first stepped surface T of the first conductive layer WL disposed in the plurality of conductive layers WL, and is connected to the first conductive layer WL and one or more lower-side conductive layers WL that are continuous with the first conductive layer WL in the stacking direction.

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