Memory structure and method for manufacturing the same

TW202634938AActive Publication Date: 2026-08-16MACRONIX INTERNATIONAL CO LTD
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Patent Information

Application Number
TW114107666
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-02-11
Filing Date
2025-03-03
Publication Date
2026-08-16
Estimated Expiration
2045-03-02

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  • Figure TWG2TA001072386_001
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  • Figure TWG2TA001072386_003
    Figure TWG2TA001072386_003
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Abstract

A memory structure is provided. The memory structure includes a stack, a plurality of first electrodes, and a plurality of second electrodes. The stack includes first levels and second levels arranged alternately, wherein the first levels include an insulating material, and the second levels include an ovonic threshold switching material. The first electrodes penetrate through the stack. The second electrodes are disposed in the second levels. Each row of the second electrodes has a continuous arc configuration.
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Claims

1. A memory structure, comprising: The stack includes a plurality of first layers and a plurality of second layers, the first layers and the second layers being alternately configured, the first layers comprising an insulating material and the second layers comprising a bidirectional threshold switching material; A plurality of first electrodes extend through the stack; and a plurality of second electrodes are disposed in the second layer, wherein each row of second electrodes has a continuous arcuate shape; wherein the continuous arcuate shape is formed by a plurality of arcuate portions connected to each other and opening in the same direction, the opening direction of the arcuate portions being opposite to the first electrodes.

2. The memory structure as described in claim 1, wherein, Between two adjacent rows of first electrodes, there are two rows of second electrodes, and corresponding arc-shaped portions from the two rows of second electrodes form part of a virtual ring.

3. The memory structure as described in claim 1, wherein, Each of the second electrodes includes an electrode layer and an arc-shaped conductor, the electrode layer being disposed on the sidewall of the arc-shaped conductor opposite to the opening direction of the arc-shaped conductor.

4. A method for manufacturing a memory structure, comprising: An initial stack is formed on a bottom layer structure by alternately forming a first layer of insulating material and a second layer of bidirectional threshold switching material on the bottom layer structure; a plurality of openings are formed through the initial stack, wherein the openings include a plurality of first openings arranged in a plurality of first rows and a plurality of second openings arranged in a plurality of second rows, the first rows and the second rows being alternately arranged; the second openings are covered; a plurality of first electrodes are formed respectively located in the first openings; the first openings having the first electrodes are covered; and a plurality of second electrodes are formed in the second layer through the second openings; wherein each row of second electrodes has a continuous arcuate shape, the continuous arcuate shape being formed by a plurality of arcuate portions connected to each other and opening in the same direction, the opening direction of the arcuate portions being opposite to the first electrodes.

5. The method for manufacturing the memory structure as described in claim 4, further comprising: Before covering the second opening, fill the opening with sacrificial material; Furthermore, the method of covering the second opening includes: forming a capping layer on the initial stack and covering the opening; and forming a masking layer on the capping layer at a position above the second opening; and the method of manufacturing the memory structure further includes: after covering the second opening, removing a portion of the capping layer on the sacrificial material in the first opening, and removing the sacrificial material in the first opening.

6. A method for manufacturing a memory structure as described in claim 4, wherein, Covering the first opening having the first electrode includes: forming a capping layer on the initial stack and covering the opening; and forming a masking layer on the capping layer at a position above the first opening having the first electrode; and wherein the method of manufacturing the memory structure further includes: filling the opening with a sacrificial material before covering the second opening; and after covering the first opening having the first electrode, removing the portion of the capping layer on the sacrificial material in the second opening, and removing the sacrificial material in the second opening.

7. The method for manufacturing a memory structure as described in claim 4, further comprising: Before forming the second electrode in the second layer through the second opening, a portion of the bidirectional threshold switch material located in the second layer is isotropically removed through the second opening to form a plurality of extended spaces in the second layer, wherein the extended spaces are connected to each other in the arrangement direction of the second row of the second opening.