Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is provided. The semiconductor device includes a bottom plate, a stack, a conductive pillar, a protecting layer and a memory layer. The stack is stacked on the bottom plate along a first direction. The stack includes insulating layers and conductive layers alternately stacked on the bottom plate along the first direction. The conductive pillar extends along the first direction and passes through at least a portion of the stack. The protecting layer extends along the first direction, surrounds the conductive pillar and is disposed between the conductive pillar and the conductive layers. A resistance of the protecting layer is higher than a resistance of the conductive layers. The memory layer surrounds the protecting layer and is disposed between the protecting layer and the conductive layers.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same. More particularly, this invention relates to memory devices and methods for manufacturing the same. Prior Technology

[0002] Recently, the demand for three-dimensional memory devices has been increasing. One type of three-dimensional memory device is the three-dimensional bidirectional threshold-switched memory (3D OTS memory). The bidirectional threshold switch uses bidirectional materials, allowing its resistance to drop significantly at a threshold voltage (Vt), forming an on state. When the voltage drops below the threshold voltage, it regains high resistance, forming a blocking state. A three-dimensional bidirectional threshold-switched memory can comprise an array of multiple memory cells stacked vertically. However, current three-dimensional bidirectional threshold-switched memories still face some electrical problems, such as the tendency to generate surge currents during memory cell reads. Summary of the Invention

[0003] This invention addresses improvements to three-dimensional bidirectional threshold switch memory (3D OTS memory), particularly reducing surge current to prevent component damage and increase system stability.

[0004] According to some embodiments, the present invention provides a semiconductor device. The semiconductor device includes a substrate and a stack. The stack is disposed on the substrate along a first direction. The stack includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked on the substrate along the first direction. Conductive pillars extend along the first direction, passing through at least a portion of the stack. A protective layer extends along the first direction, surrounds the conductive pillars, and is disposed between the conductive pillars and the conductive layers. The resistance of the protective layer is higher than the resistance of the conductive layers. A memory layer surrounds the protective layer and is disposed between the protective layer and the conductive layers.

[0005] According to some embodiments, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes the following steps: providing a substrate; forming a stack stacked on the substrate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, the insulating layers and conductive layers being alternately stacked on the substrate along the first direction; forming a conductive pillar extending along the first direction and passing through at least a portion of the stack; forming a protective layer extending along the first direction, surrounding the conductive pillar and disposed between the conductive pillar and the conductive layer, wherein the resistance value of the protective layer is higher than the resistance value of the conductive layer; forming a memory layer surrounding the protective layer and disposed between the protective layer and the conductive layer.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Simple Explanation of the Diagram

[0007] Figure 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention; Figure 2 illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present invention; Figures 3A to 3F illustrate flowcharts of the fabrication process of the semiconductor device in Figure 2; Figure 4 illustrates a cross-sectional view of a semiconductor device according to yet another embodiment of the present invention; and Figure 5 shows a cross-sectional view of the manufacturing method of the semiconductor device in Figure 4. Implementation

[0008] The following description, in conjunction with the accompanying drawings, details various embodiments. The descriptions and drawings are provided for illustrative purposes only and are not intended to be limiting. For clarity, some elements and / or symbols may be omitted in some drawings. Furthermore, elements in the drawings may not be drawn to scale. It is anticipated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further repetition.

[0009] According to some embodiments, the semiconductor device of the present invention can be applied to three-dimensional bidirectional threshold switching (OTS) memory, such as three-dimensional OTS only memory, but the present invention is not limited thereto. Three-dimensional OTS only memory uses only OTS elements, which serve as both storage units and selection elements, and does not require additional transistors or other components to control data reading and writing.

[0010] Figure 1 shows a cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention.

[0011] Referring to Figure 1, the semiconductor device 10 includes a substrate 100, a stack ST, a conductive pillar 110, a protective layer 108, and a memory layer 106. The stack ST is stacked on the substrate 100 along a first direction D1, wherein the stack ST includes a plurality of insulating layers 102 and a plurality of conductive layers 104, and the insulating layers 102 and conductive layers 104 are alternately stacked on the substrate 100 along the first direction D1. In this embodiment, the first direction D1 is, for example, parallel to the normal direction of the upper surface 100s of the substrate 100, and the bottommost and topmost layers of the stack ST are both insulating layers 102, but the present invention is not limited thereto. The conductive layer 104 is made of a conductive material, which is tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu), ruthenium (Ru), cobalt (Co), cobalt silicide (CoSiX), titanium silicide (TiSiX), nickel (Ni), nickel silicide (NiSiX), platinum (Pt), or any combination thereof. The insulating layer 102 may be made of a dielectric material, such as an oxide. In some embodiments, the conductive layer 104 may be a low-resistance conductor and may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), since ALD or CVD is a highly conformal process because it fills the space formed by the removal of the sacrificial layer 104' (as shown in Figure 5, detailed below).

[0012] The conductive post 110 extends along the first direction D1, passing through at least a portion of the stack ST. In this embodiment, the bottom surface 110bs of the conductive post 110 rests in the bottom conductive layer 104 of the stack ST, without completely penetrating the bottom conductive layer 104 of the stack ST, and without extending to the bottom insulating layer 102 of the stack ST. However, the invention is not limited thereto. The material of the conductive post 110 includes conductive materials, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu), ruthenium (Ru), cobalt (Co), cobalt silicide (CoSiX), titanium silicide (TiSiX), nickel (Ni), nickel silicide (NiSiX), platinum (Pt), or any combination thereof. In some embodiments, the conductive post 110 can be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes.

[0013] The protective layer 108 extends continuously along a first direction D1, surrounds the conductive post 110, and is disposed between the conductive post 110 and the conductive layer 104. It overlaps the insulating layer 102 and the conductive layer 104 in a second direction D2 and a third direction D3, wherein the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. Furthermore, the protective layer 108 extends further along the second direction D2 and the third direction D3, contacting the bottom surface 110bs of the conductive post 110. The resistance value of the protective layer 108 may be higher than the resistance value of the conductive layer 104 and the resistance value of the conductive post 110. In the cross-sectional view shown in Figure 1, the protective layer 108 may have a U-shaped cross-section. The material of the protective layer 108 may include a high-resistivity material, such as doped polysilicon, undoped polysilicon, silicon-germanium alloy (SiGeX), germanium (Ge), gallium nitride (GaN), indium gallium zinc oxide (IGZO), indium oxide (InO), metal oxide channel material, tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), carbon, doped carbon, graphene, or others. In some embodiments, the protective layer 108 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes.

[0014] The memory layer 106 extends along a first direction D1, surrounds the protective layer 108, and is disposed between the protective layer 108 and the conductive layer 104. In this embodiment, the memory layer 106 extends continuously along the first direction D1 and overlaps the insulating layer 102 and the conductive layer 104 on the second direction D2 and the third direction D3. The memory layer 106 further extends along the second direction D2 and the third direction D3, contacting the bottom surface of the protective layer 108, but the invention is not limited thereto. In the cross-sectional view shown in Figure 1, the memory layer 106 may have a U-shaped cross-section. Multiple memory cells may be formed at multiple intersections between the memory layer 106 and the conductive layer 104. The memory layer 106 may include memory material for storing 0 or 1. Furthermore, the memory layer 106 may serve as a bidirectional threshold switch, and its material may be, for example, arsenic triselenide (As₂Se₃), zinc telluride (ZnTe), or germanium selenide (GeSe). In some embodiments, the material of memory layer 106 may include a chalcogenide, which is incorporated with one or more elements selected from the group consisting of: tellurium (Te), indium (In), gallium (Ga), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), antimony (Sb), and phosphorus (P). In some embodiments, memory layer 106 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes. ALD or CVD is a highly conformal process because it fills the memory material into the first opening H11 (as shown in Figure 3B, detailed below). Memory layer 106 provides 0 and 1 or multilevel characteristics.

[0015] The semiconductor device 10 may further include a capping layer 112, a contact 114, and a conductor layer 116. The capping layer 112 covers the stack ST. The conductor layer 116 is disposed on the capping layer 112 and extends along a third direction D3. The contact 114 passes through the capping layer 112 and makes electrical contact with the conductive pillar 110 and the conductor layer 116. That is, the conductor layer 116 is electrically connected to the conductive pillar 110 through the contact 114.

[0016] In some embodiments, the conductive layer 104 can serve as a word line, and the conductor layer 116 can serve as a bit line.

[0017] Compared to semiconductor devices without a protective layer, the semiconductor device of this invention includes a protective layer 108, and the resistance of the protective layer 108 is higher than that of the conductive layer 104. Therefore, the protective layer 108 can reduce surge current to avoid damage to components and increase system stability. Furthermore, since the protective layer 108 surrounds the conductive post 110 and is disposed between the conductive post 110 and the conductive layer 104, the resistance can be locally increased for each memory cell, avoiding a global increase in the resistance of the bit lines or word lines.

[0018] Figure 2 illustrates a cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention. The difference between semiconductor device 20 and semiconductor device 10 is that semiconductor device 20 further includes multiple external electrode layers 118 and an internal electrode layer 120; other identical or similar parts will not be described in detail. Elements in semiconductor device 20 that are identical or similar to those in semiconductor device 10 are indicated by the same or similar element symbols and have the same or similar structure, materials, and functions.

[0019] Referring to Figure 2, the outer electrode layer 118 of the semiconductor device 20 is disposed between the conductive layer 104 and the memory layer 106. The outer electrode layer 118 surrounds the memory layer 106. The outer electrode layers 118 of different layers are separated by an insulating layer 102. The inner electrode layer 120 is disposed between the memory layer 106 and the protective layer 108, and surrounds the protective layer 108. The inner electrode layer 120 can extend continuously along a first direction D1, and overlap the insulating layer 102 and the conductive layer 104 in a second direction D2 and a third direction D3. In addition, the inner electrode layer 120 extends further along the second direction D2 and the third direction D3, contacting the bottom surface of the protective layer 108. In the cross-sectional view shown in Figure 2, the inner electrode layer 120 can have a U-shaped cross-section. The materials of the outer electrode layer 118 and the inner electrode layer 120 may each include a conductive material, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), carbon, doped carbon, graphene, or others.

[0020] In some embodiments, the outer electrode layer 118 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). ALD and CVD are highly conformal processes because they fill the pores H13 (as shown in Figure 3C, detailed below) with conductive material. The conductive layer 104 and the memory layer 106 have good interface characteristics and stable electrical-temperature characteristics. The resistance of the outer electrode layer 118 may be less than or greater than the resistance of the conductive layer 104, but less than the resistance of the protective layer 108.

[0021] In some embodiments, the inner electrode layer 120 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). ALD and CVD are highly conformal processes because they fill the first opening H11 (as shown in Figure 3B, detailed below) with conductive material. The memory layer 106 and the protective layer 108 have good interface characteristics and stable electrical-temperature characteristics. The resistance of the inner electrode layer 120 may be less than or greater than the resistance of the conductive layer 104, but less than the resistance of the protective layer 108.

[0022] The inner electrode layer 120 and the conductive pillar 110 have good interface characteristics and stable electrical temperature characteristics. The resistance of the protective layer 108 can be greater than the resistance of the outer electrode layer 118, the inner electrode layer 120, and the conductive pillar 110 to reduce surge current.

[0023] The configuration of the outer electrode layer 118 and the inner electrode layer 120 is selective, depending on the interface, temperature, electrical, or mechanical characteristics. However, the resistance of the protective layer 108 must be high enough to reduce surge current. In one embodiment, the semiconductor device includes an outer electrode layer 118 but not an inner electrode layer 120. In another embodiment, the semiconductor device includes an inner electrode layer 120 but not an outer electrode layer 118.

[0024] Compared to embodiments without an outer electrode layer 118 and an inner electrode layer 120, the outer electrode layer 118 and the inner electrode layer 120 provide better interface performance between the memory layer 106 and the conductor (e.g., conductive layer 104 or conductive pillar 110), such as better electrical interface performance, mechanical interface performance, or thermal interface performance. That is, the outer electrode layer 118 and the inner electrode layer 120 can respectively improve the electrical conductivity between the memory layer 106 and the conductor, increase the adhesion between the memory layer 106 and the conductor, or prevent metal ions in the conductor from escaping into the memory layer 106.

[0025] Figures 3A to 3F illustrate flowcharts of the fabrication method of the semiconductor device 20 in Figure 2. That is, the fabrication method of the semiconductor device 20 includes the sequential steps shown in Figures 3A to 3F.

[0026] Please refer to Figure 3A. A base plate 100 is provided, and a stack ST is formed. The stack ST is stacked on the base plate 100 along a first direction D1, wherein the stack ST includes a plurality of insulating layers 102 and a plurality of conductive layers 104, and the insulating layers 102 and conductive layers 104 are alternately stacked on the base plate 100 along the first direction D1.

[0027] Referring to Figure 3B, a first opening H11 is formed by an etching process. The first opening H11 passes through at least a portion of the stacked ST along a first direction D1. In this embodiment, the bottom of the first opening H11 rests on the bottommost insulating layer 102 of the stacked ST.

[0028] Referring to Figure 3C, multiple holes H13 are formed by an etch-back process, such as isotropic reactive ion etching (Isotropic RIE). The holes H13 connect to the first opening H11 and correspond to the conductive layer 104. That is, the etch-back process removes a portion of the conductive layer 104, causing the conductive layer 104 to recede and form holes H13 between two adjacent insulating layers 102.

[0029] Referring to Figure 3D, conductive material is filled into the holes H13, the top of the stacked ST, and the first opening H11 by a deposition process to form a conductive material layer 118'. The conductive material layer 118' conforms to the top of the stacked ST and the first opening H11. The material of the conductive material layer 118' is the same as the material of the aforementioned outer electrode layer 118, and will not be described again here.

[0030] Please refer to Figure 3E. An excess conductive material layer 118' is removed by an etching process to form an external electrode layer 118 located in the hole H13. The etching process is, for example, isotropic reactive ion etching.

[0031] Referring to Figure 3F, a memory layer 106, an inner electrode layer 120, a protective layer 108, and a conductive pillar 110 are sequentially formed in the first opening H11 (sidewalls and bottom) through multiple deposition processes. Next, a planarization process is performed to make the tops of the topmost layers of the stacked ST—the insulating layer 102, memory layer 106, inner electrode layer 120, protective layer 108, and conductive pillar 110—flush together. The planarization process is, for example, Chemical Mechanical Planarization (CMP). Multiple memory cells can be formed at multiple intersections between the memory layer 106 and the conductive layer 104. Memory cells corresponding to the same memory layer 106 are stacked in the first direction D1 to form a memory array. Multiple memory layers 106 form multiple memory arrays, and multiple memory arrays form a memory array. Then, a capping layer 112 is formed to seal the memory array. The material of the capping layer 112 is, for example, an oxide.

[0032] Subsequently, a contact 114 is formed that passes through the cover layer 112 and makes electrical contact with the conductive pillar 110, and a conductor layer 116 is disposed on the cover layer 112 and the contact 114 to form a semiconductor device 20 as shown in Figure 2.

[0033] Figure 4 illustrates a cross-sectional view of a semiconductor device 30 according to another embodiment of the present invention, omitting the contact 114 and the conductor layer 116. The difference between semiconductor device 30 and semiconductor device 20 is that the shape of the memory layer 306 in semiconductor device 30 differs from that of memory layer 106; other similar or identical parts will not be described in detail. Elements in semiconductor device 30 that are the same as or similar to those in semiconductor device 20 are indicated by the same or similar element symbols and have the same or similar structure, materials, and functions.

[0034] Please refer to Figure 4. The memory layer 306 extends discontinuously in the first direction D1 and overlaps with the conductive layer 104 in the second direction D2 and the third direction D3. Adjacent memory layers 306 are separated by an insulating layer 102.

[0035] Because the shape of memory layer 306 differs from that of memory layer 106, the fabrication method of memory layer 306 is slightly different from that of memory layer 106. For example, after forming the first opening H31 (similar to the first opening H11 in Figure 3B, and having the same formation method as the first opening H11), a hole H33 (similar to the hole H13 in Figure 3C, and having the same formation method as the hole H13) is formed. The first opening H31 passes through at least a portion of the stack ST along the first direction D1. The width of the first opening H31 in the second direction D2 may be smaller than the width of the first opening H11 in the second direction D2. The hole H33 connects to the first opening H31 and corresponds to the conductive layer 104. The width of the hole H33 in the second direction D2 may be greater than the width of the hole H13 in the second direction D2. For example, the hole H33 is formed by an isotropic etching process that etches the conductive layer 104 to form a recessed profile deeper than the first opening H11. This isotropic etching process has very high selectivity for the conductive layer 104. The insulating layer 102 remains almost intact. Subsequently, conductive material is filled into the hole H33 by deposition (e.g., ALD or CVD). Then, an isotropic etching process is performed to pull back the conductive material, forming a shallower recess than the hole H33. In other words, a portion of the conductive material is removed, exposing a portion of the hole H33 again, and the remaining portion of the conductive material forms the outer electrode layer 118. This isotropic etching process has very high selectivity for the conductive material forming the conductive layer 104. The insulating layer 102 remains almost intact. Subsequently, memory material is filled into the portion (shallow recess) of the hole H33, onto the stack ST, and into the first opening H31, forming a memory material layer (not shown) conformally to the stack ST and the first opening H31. Then, excess memory material layer (not shown) is removed by an isotropic etching process, forming the memory layer 306 in the hole H33. The isotropic etching process has very high selectivity for the memory material layer (not shown). The insulating layer 102 remains almost intact. That is, the hole H33 can accommodate the outer electrode layer 118 and the memory layer 306. After forming the memory layer 306, the inner electrode layer 120, the protective layer 108, and the conductive pillar 110 are sequentially formed in the first opening H31 using the same fabrication method as described above for the inner electrode layer 120, the protective layer 108, and the conductive pillar 110.

[0036] In one embodiment, the method for forming the stacked STs of semiconductor device 30 is the same as the method for forming the stacked STs of semiconductor device 20 described above, but the present invention is not limited thereto. In another embodiment, the method for forming the stacked STs of semiconductor device 30 is different from the method for forming the stacked STs of semiconductor device 20 described above, as shown in Figure 5.

[0037] Figure 5 shows a cross-sectional view of a method for manufacturing another embodiment of the semiconductor device 30 in Figure 4.

[0038] The steps for forming the stacked ST of the semiconductor device 30 may include the steps described below. First, a stacked structure ST' as shown in Figure 5 is formed. The stacked structure ST' includes an insulating layer 102 and a plurality of sacrificial layers 104' alternately stacked along a first direction D1, wherein the material of the insulating layer 102 may be the same as the material of the insulating layer 102 described above with respect to Figure 2, and the material of the sacrificial layer 104' may include a nitride, such as silicon nitride. After forming the conductive pillars 110 and the capping layer 112, the sacrificial layers 104' are removed by an etching process, and conductive material is filled at the location where the sacrificial layers 104' are removed to form a conductive layer 104, wherein the material of the conductive layer 104 may be the same as the material of the conductive layer 104 described above with respect to Figure 2.

[0039] It should be understood that the steps for forming the stacked ST of semiconductor devices 10-20 in Figures 1 and 2 can also be replaced by the fabrication method described in Figure 5.

[0040] In summary, this invention provides a semiconductor device and a method for manufacturing the same. Because the semiconductor device of this invention includes a protective layer, which can locally increase the resistance value of each memory cell, it can reduce surge current, protect components from damage caused by surge current, and increase the stability of the system.

[0041] While the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0042] 10~30: Semiconductor devices 100: Base Plate 100s: Top surface 102: Insulation layer 104: Conductive layer 104': Sacrificial Layer 106,306: Memory Layer 108: Protective layer 110: Conductive column 110bs: Bottom surface 112: Covering layer 114: Contact element 116: Conductor layer 118: External electrode layer 118': Conductive material layer 120: Inner Electrode Layer D1: First Direction D2: Second Direction D3: Third direction H11, H31: First opening H13, H33: Holes ST: Stacking ST': Layered structure

Claims

1. A semiconductor device, comprising: One base plate; A stack disposed on the base plate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, the insulating layers and the conductive layers being alternately stacked on the base plate along the first direction; a conductive post extending along the first direction and passing through at least a portion of the stack; a protective layer extending along the first direction, surrounding the conductive post and disposed between the conductive post and the conductive layers, wherein the resistance value of the protective layer is higher than the resistance value of the conductive layers; and a memory layer surrounding the protective layer and disposed between the protective layer and the conductive layers, wherein the memory layer serves as a bidirectional threshold switch.

2. The semiconductor device as claimed in claim 1, wherein the memory layer extends continuously along the first direction and overlaps the insulating layers and the conductive layers in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

3. The semiconductor device as claimed in claim 1, wherein the memory layer extends discontinuously in the first direction and overlaps the conductive layers in a second direction and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

4. The semiconductor device as claimed in claim 1 further includes a plurality of external electrode layers disposed between the conductive layers and the memory layer.

5. The semiconductor device as claimed in claim 4, wherein the external electrode layers surround the memory layer.

6. The semiconductor device as claimed in claim 1 further includes an internal electrode layer disposed between the memory layer and the protective layer.

7. The semiconductor device as claimed in claim 6, wherein the internal electrode layer surrounds the protective layer.

8. The semiconductor device as claimed in claim 1 further includes a conductor layer disposed on the stack and electrically connected to the conductive pillar.

9. The semiconductor device of claim 1, wherein the protective layer extends continuously along the first direction and overlaps the insulating layers and the conductive layers in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

10. A method for manufacturing a semiconductor device, comprising: Provide a base plate; A stack is formed on a base plate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, the insulating layers and the conductive layers being alternately stacked on the base plate along the first direction; a conductive post is formed extending along the first direction and passing through at least a portion of the stack; a protective layer is formed extending along the first direction, surrounding the conductive post and disposed between the conductive post and the conductive layers, wherein the resistance value of the protective layer is higher than the resistance value of the conductive layers; and a memory layer is formed surrounding the protective layer and disposed between the protective layer and the conductive layers, wherein the memory layer serves as a bidirectional threshold switch.

11. The method of manufacturing the semiconductor device as described in claim 10 further includes: A first opening is formed, the first opening passing through at least a portion of the stack along the first direction; And the memory layer and the protective layer are formed sequentially in the first opening.

12. A method of manufacturing a semiconductor device as claimed in claim 11, wherein the memory layer extends continuously along the first direction and overlaps the insulating layers and the conductive layers in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

13. The method of manufacturing the semiconductor device as described in claim 11 further includes: A plurality of holes are formed, which are connected to the first opening and correspond to the conductive layers; And fill the pores with conductive material to form a plurality of outer electrode layers.

14. The method of fabricating a semiconductor device as described in claim 11 further includes forming an internal electrode layer between the memory layer and the protective layer.

15. The method of manufacturing the semiconductor device as described in claim 10 further includes: A first opening is formed, the first opening passing through at least a portion of the stack along the first direction; A plurality of holes are formed, the holes being connected to the first opening and corresponding to the conductive layers; a conductive material is filled into the holes; a portion of the conductive material is removed to expose a portion of the holes, and the remaining portion of the conductive material forms a plurality of external electrode layers; a memory material is filled into the portion of the holes to form the memory layer; And to form the protective layer in the first opening.

16. A method of manufacturing a semiconductor device as claimed in claim 15, wherein the memory layer extends discontinuously in the first direction and overlaps the conductive layers in a second direction and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

17. The method of manufacturing a semiconductor device as described in claim 15 further includes: The pores are filled with conductive material to form a plurality of external electrode layers.

18. The method of fabricating a semiconductor device as described in claim 15 further includes forming an internal electrode layer between the memory layer and the protective layer.

19. A method of fabricating a semiconductor device as described in claim 10, wherein the step of forming the stack includes: A stacked structure is formed, the stacked structure comprising insulating layers and a plurality of sacrificial layers stacked alternately along the first direction; And remove the sacrificial layers and fill the locations where the sacrificial layers were removed with conductive material to form the conductive layers.

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