GAN power semiconductor device

Abstract

A gallium nitride (GaN) power semiconductor device includes, from bottom to top, a substrate, a gallium nitride layer, and a barrier layer. It further includes a source architecture, a drain architecture, a first gate architecture, and a second gate architecture formed on and spaced apart from each other in the barrier layer. The first gate architecture is located between the source architecture and the drain architecture and is used to control the presence or flow of a two-dimensional electron gas to conduct or block the current between the source architecture and the drain architecture. The second gate architecture is located between the first gate architecture and the drain architecture and includes a metal layer that contacts the barrier layer and is electrically connected to the source architecture. The metal layer and the barrier layer form a structure with Schottky diode characteristics. This reduces dynamic threshold voltage drift and source-drain voltage drift, thereby reducing power loss during reverse conduction.

Description

Gallium Nitride Power Semiconductor Device The present invention relates to a semiconductor device, and particularly to a gallium nitride power semiconductor device. The third-generation semiconductor materials are based on wide-bandgap composite materials (Wide Bandgap compound material), represented by silicon carbide (SiC) and gallium nitride (GaN). Due to their excellent material properties, high carrier mobility, and high bandgap, for example, the FOM of GaN components is 5 to 10 times higher than that of Si components, which gives them great potential to replace Si components in high-voltage and high-power applications, and can be applied in higher-order high-voltage power components and high-frequency communication component fields. Referring to FIGS. 1 and 2, a circuit diagram and a structural schematic diagram of a conventional gallium nitride power semiconductor device 11 are shown. The gallium nitride power semiconductor device 11 includes a substrate 111, a gallium nitride (GaN) layer 112, and a barrier layer 113 from bottom to top. A two-dimensional electron gas (2DEG) is formed between the barrier layer 113 and the gallium nitride layer 112. The gallium nitride power semiconductor device 11 further includes a source electrode structure 114, a gate electrode structure 115, and a drain electrode structure 116 formed on the barrier layer 113 at intervals. Among them, the electron channel 117 formed by the two-dimensional electron gas is represented by a dotted line. Since the gallium nitride power semiconductor device 11 does not have a body diode, when the source-drain voltage is equal to the gate-drain voltage and not lower than the threshold voltage (Vsd = Vgd >= Vth), the reverse current is conducted through the channel, and when the source-drain voltage is equal to the gate-drain voltage and less than the threshold voltage (Vsd = Vgd < Vth), the reverse current is blocked through the channel, which will cause high power loss during reverse conduction. In addition, the gallium nitride power semiconductor device 11 is also affected by the dynamic threshold voltage drift (Vth shift) and source-drain voltage drift (Vsd shift) caused by the gate charge trapping effect (Gate trapping). All of these will reduce the working current of the gallium nitride power semiconductor device 11 and cause additional reverse conduction loss. Therefore, an object of the present invention is to provide a gallium nitride power semiconductor device that can solve the above problems. Thus, the gallium nitride power semiconductor device of the present invention includes a substrate, a gallium nitride layer, a barrier layer, a source electrode structure, a drain electrode structure, a first gate electrode structure, and a second gate electrode structure. The gallium nitride layer is located on top of the substrate. The barrier layer is located above the gallium nitride layer, and a two-dimensional electron gas is formed between the barrier layer and the gallium nitride layer. The source architecture and the drain architecture are formed alternately on the barrier layer. The first gate architecture is formed on the barrier layer and located between the source architecture and the drain architecture, and is used to control the presence or flow of two-dimensional electron gas to conduct or block the current between the source architecture and the drain architecture. The second gate architecture is formed on the barrier layer and located between the first gate architecture and the drain architecture, including a metal layer that contacts the barrier layer and is electrically connected to the source architecture. The metal layer and the barrier layer form a structure with Schottky diode characteristics. The advantages of this invention are as follows: by placing the second gate architecture between the first gate architecture and the drain architecture, the voltage difference seen in the first gate architecture can be reduced, thereby mitigating the impact of the gate charge trapping effect. Furthermore, by forming a structure with Schottky diode characteristics between the metal layer and the barrier layer, functionality similar to a bulk diode can be provided. This reduces dynamic threshold voltage drift and source-drain voltage drift, and decreases power loss during reverse conduction. 2: Gallium nitride power semiconductor devices 21:Substrate 22: Gallium nitride layer 221: Electronic Channel 23: Barrier Layer 24: Source Architecture 25: Drain Architecture 26: First Gate Architecture 261: p-type gallium nitride layer 262: Conductive layer 27: Second gate architecture 271: Metal layer 28: Field board 31: First transistor 32: Second transistor 33: Schottky Diode 91~96: Curve Isd: Source / Drain Current Vsd: Source / Drain Voltage Ids: Drain current Vgs: Gate-source voltage Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: Figure 1 is a circuit diagram of a conventional gallium nitride power semiconductor device; Figure 2 is a structural schematic diagram of the conventional gallium nitride power semiconductor device; Figure 3 is an equivalent circuit diagram of an embodiment of the gallium nitride power semiconductor device of the present invention; Figure 4 is a structural schematic diagram of the embodiment; Figure 5 is a graph of source-drain current versus source-drain voltage, illustrating the analog curve of the embodiment and the conventional one; and Figure 6 is a graph of source-drain current versus gate-source voltage, illustrating the analog curve of the embodiment and the conventional one. Referring to Figures 3 and 4, one embodiment of the gallium nitride power semiconductor device 2 of the present invention includes a substrate 21, a gallium nitride layer 22, a barrier layer 23, a source structure 24, a drain structure 25, a first gate structure 26, and a second gate structure 27. The main material of the substrate 21 is sapphire (Al₂O₃). 2O 3) Silicon carbide (SiC) or silicon (Si). The gallium nitride (GaN) layer 22 is located above the substrate 21. The barrier layer 23 is located above the gallium nitride layer 22. A high-density, high-mobility electron channel, i.e., a two-dimensional electron gas (2DEG), is formed at the heterostructure interface between the barrier layer 23 and the gallium nitride layer 22. The barrier layer 23 is made of aluminum gallium nitride (AlGaN). For example, the barrier layer 23 is made of Al... X Ga 1-X N, where 0 X 1. Among them, the electron channel 221 formed by the two-dimensional electron gas is represented by a dashed line. The source architecture 24 and the drain architecture 25 are formed alternately on the barrier layer 23. The source architecture 24 and the drain architecture 25 are made of nickel-gold stack (Ni / Au), titanium-aluminum stack (Ti / Al), or titanium nitride (TiN), and ohmic contacts are formed between the source architecture 24 and the barrier layer 23, and between the drain architecture 25 and the barrier layer 23. The first gate architecture 26 is formed on the barrier layer 23 and located between the source architecture 24 and the drain architecture 25, and is used to control the presence or flow of a two-dimensional electron gas to conduct or block the current between the source architecture 24 and the drain architecture 25. The first gate architecture 26 includes a p-type gallium nitride layer 261 formed on the barrier layer 23 and a conductive layer 262 located above the p-type gallium nitride layer 261. The second gate architecture 27 is formed on the barrier layer 23 and located between the first gate architecture 26 and the drain architecture 25. It includes a metal layer 271 that contacts the barrier layer 23 and is electrically connected to the source architecture 24. The metal layer 271 and the barrier layer 23 form a structure with Schottky diode characteristics. That is, a Schottky contact is formed between the metal layer 271 and the barrier layer 23. It is worth noting that by placing the second gate architecture 27 between the first gate architecture 26 and the drain architecture 25, the voltage difference seen by the first gate architecture 26 can be reduced. To further explain, without the second gate architecture 27, the first gate architecture 26 directly bears the voltage difference between the drain architecture 25 and the first gate architecture 26, resulting in a more severe gate trapping effect. However, with the second gate architecture 27, the first gate architecture 26 sees the voltage difference between itself and the second gate architecture 27, which is significantly smaller than the voltage difference between the drain architecture 25 and the first gate architecture 26, thus reducing the impact of the gate trapping effect. Furthermore, the metal layer 271 of the second gate architecture 27 is composed of metal or a metal compound, and its high conductivity significantly reduces the charge trapping effect. Therefore, the second gate architecture 27 is not affected by the voltage difference between the drain architecture 25 and the second gate architecture 27. Both the first gate architecture 26 and the second gate architecture 27 have adjustable dimensions in both the horizontal (W) and vertical (L) directions. They only need to meet the voltage and current handling requirements of the power device, and the horizontal (W) length of the first gate architecture 26 must not be less than the horizontal (W) length of the second gate architecture 27. It is worth noting that since the second gate architecture 27 generates capacitance, this capacitance can be reduced by decreasing its horizontal (W) length. For example, the horizontal (W) length of the second gate architecture 27 can be designed to be shorter than that of the first gate architecture 26, and the horizontal (W) length of the second gate architecture 27 can be segmented and spaced at predetermined ratios, while its overall length remains approximately the same as that of the first gate architecture 26. This achieves the aforementioned benefits while reducing the capacitance generated by the second gate architecture 27. The field plate 28 is located above the source architecture 24, the first gate architecture 26, and the second gate architecture 27, and extends toward the drain architecture 25. The field plate 28 is made of aluminum (Al) or copper (Cu). The metal layer 271 is electrically connected to the source architecture 24 via the field plate 28. The equivalent circuit formed by the above architecture has a first transistor 31, a second transistor 32, and a Schottky diode 33. The first transistor 31 is an enhancement-mode GaN HEMT (or E-mode GaN HEMT). The second transistor 32 is a depletion-mode GaN HEMT (or D-mode GaN HEMT). Both the first transistor 31 and the second transistor 32 are power devices. In this configuration, the source architecture 24 and the drain architecture 25 serve as the source of the first transistor 31 and the drain of the second transistor 32, respectively. The first gate architecture 26 serves as the gate of the first transistor 31. The second gate architecture 27 serves as the gate of the second transistor 32, and the metal layer 271 and the barrier layer 23 effectively form the Schottky diode 33. The Schottky diode 33 serves as a body Schottky diode, providing functionality similar to a body diode. The drain of the first transistor 31 is electrically connected to the source of the second transistor 32, the gate of the second transistor 32 is electrically connected to the cathode of the Schottky diode 33, and the anode of the Schottky diode 33 is electrically connected to the source of the first transistor 31. In this embodiment, the threshold voltage (Vth) of the first transistor 31 is about 1.5V, the drift (Vth shift) during operation is about 1V, the threshold voltage of the second transistor 32 is about -2V, and the forward voltage of the Schottky diode 33 is about 0.8V. Referring to Figures 3-6, Figure 5 shows a graph of the source-to-drain current (Isd) versus the source-to-drain voltage (Vsd) of the gallium nitride power semiconductor device 2. Curve 91 is the ideal simulation curve of a conventional gallium nitride power semiconductor device (Figures 1 and 2), curve 92 is the operational simulation curve of a conventional gallium nitride power semiconductor device, and curve 93 is both the ideal simulation curve and the operational simulation curve of the gallium nitride power semiconductor device 2 in this embodiment (the two lines are close together and therefore represented by the same line). As can be seen from the distance between curves 91 and 92 in Figure 5, the conventional gallium nitride power semiconductor device exhibits a large source-to-drain voltage shift (Vsd shift) during operation, while the gallium nitride power semiconductor device 2 in this embodiment shows almost no source-to-drain voltage shift. Figure 6 is a graph showing the drain-to-source current (Ids) versus gate-to-source voltage (Vgs) of the gallium nitride (GaN) power semiconductor device 2. Curve 94 represents the ideal simulation curves of a conventional GaN power semiconductor device and the GaN power semiconductor device 2 of this embodiment (the two lines are close and represented by the same curve). Curve 95 represents the operational simulation curve of a conventional GaN power semiconductor device, and curve 96 represents the operational simulation curve of the GaN power semiconductor device 2 of this embodiment. As can be seen from Figure 6, the distance between curve 95 and curve 94 is significantly greater than the distance between curve 96 and curve 94. That is, the threshold voltage shift (Vth shift) of the conventional GaN power semiconductor device during operation is significantly greater than the threshold voltage shift of the GaN power semiconductor device 2 of this embodiment during operation. Based on the above explanation, the effects of this embodiment are as follows: First, by providing the second gate architecture 27 between the first gate architecture 26 and the drain architecture 25, the voltage difference seen in the first gate architecture 26 can be reduced, thereby mitigating the impact of the gate charge trapping effect. Furthermore, by forming a structure with Schottky diode characteristics between the metal layer 271 and the barrier layer 23, a bulk Schottky diode can be integrated into the gallium nitride power semiconductor device 2 to provide functionality similar to a bulk diode. Therefore, this embodiment can reduce dynamic threshold voltage drift and source-drain voltage drift, and reduce power loss during reverse conduction. Second, by setting up the field plate 28, the electric field distribution can be improved and the performance of the gallium nitride power semiconductor device 2 can be enhanced. In summary, the gallium nitride power semiconductor device of the present invention does indeed achieve the purpose of the present invention. However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention. 2: Gallium nitride power semiconductor devices 21:Substrate 22: Gallium nitride layer 221: Electronic Channel 23: Barrier Layer 24: Source Architecture 25: Drain Architecture 26: First Gate Architecture 261: p-type gallium nitride layer 262: Conductive layer 27: Second gate architecture 271: Metal layer 28: Field board

Claims

1. A gallium nitride (GaN) power semiconductor device includes: a substrate; a GaN layer located above the substrate; a barrier layer located above the GaN layer, with a two-dimensional electron gas formed between the barrier layer and the GaN layer; a source structure and a drain structure formed alternately on the barrier layer; a first gate structure formed on the barrier layer and located between the source structure and the drain structure, used to control the presence or flow of the two-dimensional electron gas to conduct or block current between the source structure and the drain structure; a second gate structure formed on the barrier layer and located between the first gate structure and the drain structure, including a metal layer contacting the barrier layer and electrically connected to the source structure, the metal layer and the barrier layer forming a structure with Schottky diode characteristics; and a field plate located above the source structure, the first gate structure, and the second gate structure, and extending toward the drain structure, the metal layer being electrically connected to the source structure via the field plate; wherein... The equivalent circuit formed by the substrate, the gallium nitride layer, the barrier layer, the source architecture, the drain architecture, the first gate architecture, and the second gate architecture has a first transistor, a second transistor, and a Schottky diode. The source architecture and the drain architecture serve as the source of the first transistor and the drain of the second transistor, respectively. The first gate architecture serves as the gate of the first transistor, and the second gate architecture serves as the gate of the second transistor. The metal layer and the barrier layer effectively form the Schottky diode. The drain of the first transistor is electrically connected to the source of the second transistor, the gate of the second transistor is electrically connected to the cathode of the Schottky diode, and the anode of the Schottky diode is electrically connected to the source of the first transistor. The gallium nitride power semiconductor device as described in claim 1, wherein... The first gate architecture includes a p-type gallium nitride layer formed on the barrier layer and a conductive layer located above the p-type gallium nitride layer. The gallium nitride power semiconductor device as described in claim 1, wherein... The barrier layer is made of Al. X Here 1-X N, where 0 ≤ X ≤ 1. The gallium nitride power semiconductor device as described in claim 1, wherein... The source architecture and the barrier layer, as well as the drain architecture and the barrier layer, all form ohmic contacts. The gallium nitride power semiconductor device as described in claim 1, wherein... The substrate is made of sapphire, silicon carbide, or silicon.

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