Laterally-diffused metal-oxide semiconductor (LDMOS) devices including superlattice trench liner and related methods
TW202634964APending Publication Date: 2026-08-16ATOMERA INC
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Patent Information
- Application Number
- TW114141650
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-10-29
- Filing Date
- 2025-10-28
- Publication Date
- 2026-08-16
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Abstract
A laterally-diffused metal-oxide semiconductor (LDMOS) device may include a semiconductor layer having a trench therein, and a superlattice liner in the trench. The superlattice liner may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The LDMOS may further include a shallow trench isolation (STI) region within the trench, spaced-apart source and drain regions in the semiconductor layer on opposite sides of the trench, a gate on the semiconductor layer between the source and drain regions, and a drift region in the semiconductor layer surrounding the trench and separated from the STI region by the superlattice liner.
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