Vertical power semiconductor device
Patent Information
- Application Number
- TW114105193
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-12
- Publication Date
- 2026-08-16
- Estimated Expiration
- 2045-02-11
AI Technical Summary
Conventional silicon power semiconductor devices face limitations in reducing on-resistance (Ron) during conduction and reverse leakage current, which are crucial for efficient power management in industries like 5G, geostationary Earth orbit, and AI servers.
A vertical power semiconductor device design featuring a semiconductor substrate with notches and specific doping regions, along with increased thickness and depth of dielectric layers, to enhance forward current and reduce electric field strength, thereby minimizing on-resistance and leakage current.
The design increases forward current, reduces on-resistance, lowers electric field strength, and decreases reverse leakage current, improving switching performance and breakdown voltage, particularly under high voltage and frequency conditions.
Smart Images
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Abstract
Description
Technical Field
[0001] This invention relates to a power semiconductor device, and more particularly to a vertical power semiconductor device. Prior Technology
[0002] The power processors (converters / inverters) in industries such as 5G, geostationary Earth orbit, and even artificial intelligence (AI) servers all require a large number of power semiconductor devices to perform the switching operations of circuits. Therefore, power semiconductor devices play a crucial role in these industries. Those familiar with power semiconductor devices know that conduction loss and switching loss occur during the switching process. Thus, power is lost within the power semiconductor device between the switching on and off of the power processor.
[0003] Generally, power semiconductor devices require low on-resistance (Ron) during conduction to reduce power consumption across the resistor, and low reverse leakage current during off-resistance to minimize additional power loss. However, conventional silicon (Si) power semiconductor devices can no longer meet these electrical characteristics. Third-generation semiconductors (such as SiC) have wide bandgap properties that help resist high breakdown voltages; therefore, vertical power semiconductors made of SiC have been developed.
[0004] Referring to Figure 1, a conventional vertical power semiconductor device (hereinafter referred to as Case 1) 1 includes a semiconductor substrate 11 with N-type carriers and a drain contact formed under the semiconductor substrate 11. The semiconductor epitaxial layer 12 comprises a metal layer 12, a semiconductor epitaxial layer 13 formed on the semiconductor substrate 11 and having N-type carriers, a well 14 disposed within the semiconductor epitaxial layer 13 and close to an upper surface 131 of the semiconductor epitaxial layer 13 and having P-type carriers, a source electrode 15 disposed within the well 14 and close to the upper surface 131 of the semiconductor epitaxial layer 13 and having N-type carriers, two gate cells 17 disposed on the upper surface 131 of the semiconductor epitaxial layer 13, a source contact metal layer 18 on the upper surface 131 of the semiconductor epitaxial layer 13 and partially covering the gate cells 17 and connecting the source electrode 15, and two current spreading regions 19 disposed in the semiconductor epitaxial layer 13 and close to the upper surface 131 and containing N-type carriers. The well 14 has a first doped region 141 and a second doped region 142 within the first doped region 141. The source 15 is located on opposite sides of the second doped region 142. Each gate unit 17 has an upper surface 131 covering the semiconductor epitaxial layer 13, a gate dielectric layer 171 covering the first doped region 141 and partially covering the source 15, a gate 172 stacked on the gate dielectric layer 171, and an insulating layer 173 covering the gate 172. Each current diffusion region 19 is located under the respective gate dielectric layer 171 and is connected to opposite sides of the first doped region 141 of the well 14. The doping concentration of the N-type carriers in each current diffusion region 19 is five times that of the N-type carriers in the semiconductor epitaxial layer 13.
[0005] While the first design can reduce the on-resistance (Ron) during operation through the current diffusion region 19, the reduction in on-resistance (Ron) during actual operation is limited. Therefore, there is still room for improvement in the contribution of the first design to reducing on-resistance (Ron).
[0006] As explained above, improving the structure of vertical power semiconductor devices to effectively reduce on-resistance is a problem that needs to be solved by relevant industry players in this field. Summary of the Invention
[0007] Therefore, the object of the present invention is to provide a vertical power semiconductor device that can effectively reduce on-resistance.
[0008] Therefore, the vertical power semiconductor device of the present invention includes a semiconductor substrate containing a first conductivity type carrier, a semiconductor layer formed on the semiconductor substrate and containing the first conductivity type carrier, a well located in the semiconductor layer and containing a second conductivity type carrier opposite to the first conductivity type carrier, a source containing the first conductivity type carrier, two gate components disposed at intervals from each other, a source contact layer, and two current diffusion regions located in the semiconductor layer and containing the first conductivity type carrier.
[0009] The semiconductor layer has two spaced-apart notches located near the top surface of the semiconductor substrate at a depth direction from one of its top surfaces.
[0010] The well includes a first doped region close to the top surface, and a second doped region within the first doped region and close to the top surface.
[0011] The source is located within the first doped region of the well to be close to the top surface, and is separated into two source regions spaced apart from each other by the second doped region.
[0012] The two gate components are disposed at a distance from each other on the top surface of the semiconductor layer and on opposite sides of the second doped region. Each gate component includes a dielectric layer, a gate layer stacked on the dielectric layer, and an insulating film covering the gate layer. Each dielectric layer fills its corresponding gap and covers the first doped region and partially covers its corresponding source region.
[0013] The source contact layer covers and contacts the source regions, the second doped region, and the insulating film.
[0014] Each current diffusion region includes a first region corresponding to the respective notch, and a second region extending from the first region toward the first doped region to cover the first doped region. The first region is located at a first depth within the semiconductor layer that is greater than the second doped region is located at a depth within the semiconductor layer, and the second region is located at a second depth within the semiconductor layer that is greater than the first depth.
[0015] The advantage of this invention is that the design of the second region of each current diffusion region covering the first doped region of the well and the second depth being greater than the first depth of its first region helps to increase the forward current of the device during operation to reduce the on-resistance (Ron), and the design of these gaps in the semiconductor layer can also reduce the electric field strength of the device during operation due to the increased thickness of the dielectric layer filling it, which helps to reduce the reverse leakage current. Simple Explanation of the Diagram
[0016] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG1 is a front view schematic diagram illustrating a conventional vertical power semiconductor device (i.e., the present invention 1); FIG2 is a front view schematic diagram illustrating an embodiment of the vertical power semiconductor device of the present invention; FIG3 is a forward current versus forward voltage curve illustrating an electrical comparison between the present invention 1 and the embodiment of the present invention; FIG4 is an electric field versus distance curve illustrating an electrical comparison between the present invention 1 and the embodiment of the present invention; FIG5 is a reverse leakage current versus drain-source voltage curve illustrating an electrical comparison between the present invention 1 and the embodiment of the present invention; FIG6 is a gate-to-drain capacitance (CGD) versus drain-source voltage (VDS) curve illustrating an electrical comparison between the present invention 1 and the embodiment of the present invention; and FIG7 is a drain-source current (ID) versus gate-to-source voltage (VG) curve illustrating an electrical comparison between the present invention 1 and the embodiment of the present invention. Implementation
[0017] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.
[0018] Referring to Figure 2, an embodiment of the vertical power semiconductor device of the present invention includes a semiconductor substrate 2 containing a first conductivity type carrier, a semiconductor layer 3 formed on the semiconductor substrate 2 and containing the first conductivity type carrier, a well 4 located within the semiconductor layer 3 and containing a second conductivity type carrier opposite to the first conductivity type carrier, a source 5 containing the first conductivity type carrier, two gate components 6 spaced apart from each other, a source contact layer 7, two current diffusion regions 8 located within the semiconductor layer 3 and containing the first conductivity type carrier, and a drain contact layer 9 formed under the semiconductor substrate 2. In this embodiment of the present invention, the first conductivity type carrier and the second conductivity type carrier are illustrated using N-type carriers and P-type carriers as examples, respectively, but are not limited thereto. It should be noted that those skilled in the art of power semiconductor devices know that the most common power semiconductor device is the metal-oxide-semiconductor field-effect transistor (MOSFET). The basic structure of a transistor includes a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a source electrode and a well electrode within the semiconductor layer, a dielectric layer on the semiconductor layer, a gate electrode and an insulating layer, a source electrode contact connecting the source electrode and the well electrode, and a drain electrode contact located beneath the semiconductor substrate. It should be understood that a power semiconductor device is composed of a plurality of transistors arranged in a two-dimensional array. Therefore, in this embodiment of the invention, only two gate components 6 are used as an example for illustration, but the invention is not limited thereto. The applicant hereby clarifies this further.
[0019] The semiconductor layer 3 has two spaced-apart notches 310 recessed from its top surface 31 toward the semiconductor substrate 2 in a depth direction Z. In this embodiment of the invention, the semiconductor layer 3 is a silicon carbide (SiC) epitaxial layer prepared by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), and the semiconductor substrate 2 is a silicon carbide substrate.
[0020] The well 4 includes a first doped region 41 close to the top surface 31, and a second doped region 42 within the first doped region 41 and close to the top surface 31.
[0021] The source 5 is located within the first doped region 41 of the well 4, close to the top surface 31, and is separated into two source regions 51 spaced apart from each other by the second doped region 42.
[0022] The two gate components 6 are disposed at intervals on the top surface 31 of the semiconductor layer 3 and located on opposite sides of the second doped region 42. Each gate component 6 includes a dielectric layer 61, a gate layer 62 stacked on the dielectric layer 61, and an insulating film 63 covering the gate layer 62. Each dielectric layer 61 fills its corresponding gap 310 and covers the first doped region 41 and partially covers its corresponding source region 51. In this embodiment of the invention, the gate layer 62 is illustrated using a polycrystalline silicon layer as an example, and the dielectric layer 61 and the insulating film 63 are illustrated using an oxide as an example, but are not limited thereto.
[0023] The source contact layer 7 covers and contacts the source regions 51, the second doped region 42, and the insulating film 63.
[0024] Each current diffusion region 8 includes a first region 81 corresponding to each of the notches 310, and a second region 82 extending from the first region 81 toward the first doped region 41 to cover the first doped region 41. Each current diffusion region 8 also includes a third region 83, a fourth region 84, and a fifth region 85 sequentially stacked under their respective second regions 82 along the depth direction Z. The doping concentration of the first conductivity type carrier (i.e., N-type carrier) in each current diffusion region 8 is at least five times the doping concentration of the N-type carrier in the semiconductor layer 3, and the doping concentrations of the first region 81, second region 82, third region 83, fourth region 84, and fifth region 85 are substantially the same. To effectively increase the forward current and reduce the on-resistance (Ron) during actual operation of this embodiment, the first depth of each first region 81 within the semiconductor layer 3 is greater than the depth of the second doped region 42 within the semiconductor layer 3, and the second depth of each second region 82 within the semiconductor layer 3 is greater than the first depth.
[0025] It is worth mentioning that, based on the fact that each current diffusion region 8 can increase the forward current of the device during operation, the electric field strength of the dielectric layer 61 of each gate component 6 increases, which in turn affects the breakdown voltage of the device. Therefore, in order to effectively increase the forward current during operation and avoid a severe drop in its breakdown voltage in this embodiment of the invention, the depth difference between the first depth of each first region 81 and the second depth of each second region 82 is between 0.2 μm and 0.3 μm, and the depth difference between each second region 82 and the third region 83, between each third region 83 and the fourth region 84, and between each fourth region 84 and the fifth region 85 is between 0.2 μm and 0.3 μm. Furthermore, the width of the second region 82, the third region 83, the fourth region 84, and the fifth region 85 of each current diffusion region 8 decreases along the width direction W transverse to the depth direction Z, so that the outline of the second region 82, the third region 83, the fourth region 84, and the fifth region 85 of each current diffusion region 8 distributed in the semiconductor layer 3 is in a stepped shape as shown in Figure 2.
[0026] Given that the structural design of the first region 81 and the second region 82 of the current diffusion regions 8 in this embodiment of the present invention can increase the electric field strength of the dielectric layer 61 of the gate components 6 due to the increased forward current during operation, this embodiment of the present invention provides notches 310 on the top surface 31 of the semiconductor layer 3 and at the location corresponding to the dielectric layer 61 of the gate components 6. These notches fill the corresponding notches 310, thereby increasing the thickness of the dielectric layer 61 along the depth direction Z, thus reducing the reverse leakage current during actual operation. It should be noted that when the thickness of the dielectric layer 61 is insufficient, its contribution to reducing the electric field strength is limited; when the thickness of the dielectric layer 61 is too large, it also affects the smoothness of channel reversal during operation. Therefore, in this embodiment of the present invention, each notch 310 has a notch depth along the depth direction Z from the top surface 31, and the notch depth is between 0.05 μm and 0.15 μm. In this embodiment of the present invention, the notch depth is described as 0.1 μm as an example, and the thickness of the dielectric layer 61 located at each notch 310 is described as 0.05 μm as an example, but it is not limited thereto. That is, in this embodiment of the present invention, the thickness of the dielectric layer 61 located at each notch 310 is described as 0.15 μm as an example, but it is not limited thereto.
[0027] It should be further explained here that, in order to effectively reduce the electric field strength during actual operation of this embodiment, the smoothness of channel reversal must also be considered. Therefore, the total area of the first region 81 and the second region 82 of each current diffusion region 8 obtained by projecting a downward orthographic projection from above the vertical power semiconductor device of this embodiment is defined as A1, and the area of each notch 310 obtained by projecting a downward orthographic projection from directly above the vertical power semiconductor device is defined as A2, where A2 / A1 is between 0.15 and 0.3. In this embodiment of the present invention, the total area A1 of the first region 81 and the second region 82 of each current diffusion region 8 is 2 mm2, and the area A2 of each notch 310 is 0.38 mm2.
[0028] As shown in Figure 3, the forward current of this embodiment of the present invention is higher than that of the previous one, indicating that its on-resistance (Ron) is lower than that of the previous one. The results in Figure 3 confirm that the design of the second region 82 of each current diffusion region 8 of the present invention covering the first doped region 41 of the well 4 and having a second depth greater than the first depth of its first region 81, and the design of the third region 83, the fourth region 84 and the fifth region 85 stacked sequentially under the second region 82, can improve the forward current of the device during operation, and therefore its on-resistance (Ron) is lower than that of the previous one.
[0029] As shown in Figure 4, the electric field analyzed from the distance along line A-A' shown in Figure 1 (the previous case 1) gradually increases when the gate dielectric layer 171 contacts the first doped region 141, reaches saturation when it contacts the right half of the source region 15, and drops rapidly at the junction of the source region 15 and the second doped region 142; wherein, the electric field of the gate dielectric layer 171 located in the current diffusion region 19 is still as high as 2.4 × 10⁶ V / cm. In contrast, in this embodiment of the present invention, the electric field analyzed from the distance along line A-A' shown in Figure 2 also gradually increases when the dielectric layer 61 contacts the first doped region 41, reaches saturation when it contacts the right half of the source region 51, and drops rapidly at the junction of the source region 51 and the second doped region 42; however, the electric field in the dielectric layer 61 within the notch 310 is lower than 4 × 10⁵ V / cm, which is much lower than that in the previous case 1. The analysis results in Figure 4 confirm that the design of the notches 310 in the semiconductor layer 3 of this embodiment of the present invention can reduce the electric field strength of the device during operation due to the increased thickness of the dielectric layer 61 filled in the notches 310. It is expected that the reverse leakage current of this embodiment should be lower than that of the previous case 1.
[0030] As shown in Figure 5, the reverse leakage current of the previous case 1 is indeed higher than that of this embodiment of the present invention. The analysis results in Figure 5 demonstrate that this embodiment has a superior ability to resist reverse leakage current compared to the previous case 1.
[0031] Those familiar with the power semiconductor device industry know that power semiconductor devices typically operate under high voltage (e.g., at least greater than 650V) and high frequency conditions. Even a slight increase in the parasitic capacitance (CGD) generated when a power semiconductor device operates under high voltage conditions affects the speed of the component during high-frequency switching. As shown in Figure 6, the CGD-VDS curve indicates that the parasitic capacitance of this embodiment of the invention shows a trend lower than that of the previous design after VDS approaches 400V, and is approximately 20 pF / cm² lower than that of the previous design even when VDS reaches 1000V. Therefore, the switching performance of this embodiment of the invention is superior to that of the previous design in actual operation.
[0032] Since the inversion region of an N-type MOSFET is located between its P-well and its gate dielectric layer, the thickness of the gate dielectric layer determines the smoothness of the N-type MOSFET's inversion. As shown in Figure 7, the ID-VG curves indicate that the threshold voltage (Vth) of the first-party application 1 is approximately 2.5V when the thickness of its gate dielectric layer 171 is 0.05μm, while the Vth increases significantly to 3.1V when the thickness of its gate dielectric layer 171 is increased to 0.1μm. This demonstrates that the smoothness of the inversion of the device channel in the first-party application 1 is adversely affected after the thickness of its gate dielectric layer 171 is increased to 0.1μm. In contrast, the ID-VG curve of this embodiment of the invention shows that when the thickness of the dielectric layer 61 is 0.15 μm (that is, the thickness of the dielectric layer 61 at each notch 310 is 0.1 μm, and the thickness of the dielectric layer 61 without notches 310 is still 0.05 μm), the Vth is only about 2.55 V, which is close to the Vth corresponding to the previous embodiment when the thickness of its gate dielectric layer 171 is 0.05 μm. Compared with the previous embodiment when the thickness of its gate dielectric layer 171 is 0.1 μm, this shows that the smoothness of the device channel reversal in this embodiment of the invention is not adversely affected, and the increased thickness of the dielectric layer 61 at each notch 310 can reduce the electric field strength of the device during operation and reduce the reverse leakage current.
[0033] In summary, the design of the second region 82 of each current diffusion region 8 of the vertical power semiconductor device of the present invention, which covers the first doped region 41 of the well 4 and has a second depth greater than the first depth of its first region 81, and the design of the third region 83, the fourth region 84 and the fifth region 85 stacked sequentially under the second region 82, can improve the forward current of the device during operation to reduce the on-resistance (Ron), and the design of the notches 310 of the semiconductor layer 3 can also reduce the electric field strength of the device during operation and reduce the reverse leakage current due to the increased thickness of the dielectric layer 61 filling it. Therefore, the purpose of the present invention can indeed be achieved.
[0034] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification of the present invention shall still fall within the scope of the patent of the present invention.
[0035] 1: Traditional vertical power semiconductor devices
[0036] 11: Semiconductor substrate
[0037] 12: Drain contact metal layer
[0038] 13: Semiconductor epitaxial layer
[0039] 131: Upper surface
[0040] 14: Well
[0041] 141: First doped region
[0042] 142: Second doped region
[0043] 15: Source
[0044] 17: Gate Unit
[0045] 171: Gate dielectric layer
[0046] 172: Gate
[0047] 173: Insulation layer
[0048] 18: Source contact metal layer
[0049] 19: Current diffusion region
[0050] 2: Semiconductor substrate
[0051] 3: Semiconductor layer
[0052] 31: Top surface
[0053] 310: Gap
[0054] 4: Well
[0055] 41: First doped region
[0056] 42: Second doped region
[0057] 5: Source
[0058] 51: Source Region
[0059] 6: Gate assembly
[0060] 61: Dielectric layer
[0061] 62: Gate layer
[0062] 63: Insulating film
[0063] 7: Source contact layer
[0064] 8: Current diffusion region
[0065] 81: Zone 1
[0066] 82: Second District
[0067] 83: Third District
[0068] 84: Fourth District
[0069] 85: Fifth District
[0070] 9: Drain Contact Layer
[0071] W: Width direction
[0072] Z: Depth direction
Claims
1. A vertical power semiconductor device, comprising: a semiconductor substrate containing first conductivity type carriers; a semiconductor layer formed on the semiconductor substrate and containing the first conductivity type carriers, the semiconductor layer having two spaced-apart notches adjacent to the top surface recessed from a top surface toward a depth direction of the semiconductor substrate; a well located within the semiconductor layer and containing second conductivity type carriers opposite to the first conductivity type carriers, the well including a first doped region adjacent to the top surface and a second doped region within the first doped region and adjacent to the top surface; and a source located within the first doped region of the well, adjacent to the top surface, containing the first conductivity type carriers, and separated by the second doped region into two spaced-apart source regions. Two gate components are disposed at intervals on the top surface of the semiconductor layer and on opposite sides of the second doped region. Each gate component includes a dielectric layer, a gate layer stacked on the dielectric layer, and an insulating film covering the gate layer. Each dielectric layer fills its corresponding notch and covers the first doped region and partially covers its corresponding source region. A source contact layer covers and contacts the source regions, the second doped region, and the insulating film. Two current diffusion regions are located within the semiconductor layer and contain first conductivity type carriers. Each current diffusion region includes a first region corresponding to its respective notch and a second region extending from the first region toward the first doped region to cover the first doped region. A first depth of each first region within the semiconductor layer is greater than a depth of each second doped region within the semiconductor layer, and a second depth of each second region within the semiconductor layer is greater than the first depth.
2. The vertical power semiconductor device as claimed in claim 1, wherein, Each notch has a notch depth along the depth direction from the top surface, and the notch depth is between 0.05 μm and 0.15 μm.
3. The vertical power semiconductor device as claimed in claim 1, wherein, The total area of the first and second current diffusion regions, obtained by projecting a downward orthographic projection from above the vertical power semiconductor device, is defined as A1, and the area of each notch, obtained by projecting a downward orthographic projection from directly above the vertical power semiconductor device, is defined as A2, where A2 / A1 is between 0.15 and 0.
3.
4. The vertical power semiconductor device as claimed in claim 1, wherein, Each current diffusion region also includes a third region, a fourth region, and a fifth region stacked sequentially below their respective second regions along the depth direction.
5. The vertical power semiconductor device as claimed in claim 1, wherein, The depth difference between the first depth and the second depth is between 0.2 μm and 0.3 μm.
6. The vertical power semiconductor device as claimed in claim 4, wherein, The depth difference between each of the second and third zones, between each of the third and fourth zones, and between each of the fourth and fifth zones is between 0.2 μm and 0.3 μm.
7. The vertical power semiconductor device as claimed in claim 4, wherein, The width of the second, third, fourth, and fifth current diffusion regions decreases along the depth direction in a width direction transverse to the depth direction, so that the outline of the second, third, fourth, and fifth current diffusion regions distributed in the semiconductor layer is stepped.