Integrated circuit device and manufacturing method thereof

Abstract

A dual-gate thin film transistor with source, drain, and top gate structures that may be fabricated simultaneously. Each structure includes a conductive semiconductor layer, a gate dielectric layer, and a conductive core. The source and drain structures are made to function as sources and drains by positioning vias to directly contact the conductive semiconductor layer. The top gate structures are made to function as top gate electrodes by positioning vias to contact the conductive cores while avoiding contact with the conductive semiconductor layers. Differences in via width, differences between the widths of the source / drain structures and the width of the top gate structure, or differences in via alignment may be used to achieve conductive semiconductor layer contact for the source / drain structures while avoiding semiconductor layer contact for the top gate structures.

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