Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a top metal layer disposed on the substrate, a top dielectric layer disposed on the substrate and the top metal layer, at least one opening disposed in the top dielectric layer, and an aluminum layer conformally deposited on the top dielectric layer and in the at least one opening. When viewed from above, the at least one opening has a regular n-gon pattern (n is greater than or equal to

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure suitable for use in embedded high voltage (eHV) devices and processes. [Previous Technology]

[0002] In the embedded high voltage (eHV) process, square openings are designed in the top dielectric layer covering the top metal trace to expose part of the top metal trace. However, these square openings cause poor step coverage of the subsequently filled aluminum metal layer and passivation layer at the corners of the square openings. Cracks appear in the passivation layer, and acid seeps in from the cracks during the subsequent wet etching process, causing the underlying aluminum metal layer to be over-etched.

[0003] Therefore, this technical field still needs an improved semiconductor structure to solve the above-mentioned technical problems. [Summary of the Invention]

[0004] The main objective of this invention is to provide an improved semiconductor structure suitable for use in embedded high voltage (eHV) devices and processes, in order to overcome the shortcomings or disadvantages of the prior art.

[0005] In one aspect, the present invention provides a semiconductor structure comprising: a substrate; a top metal layer disposed on the substrate; a top dielectric layer disposed on the substrate and the top metal layer; at least one opening disposed in the top dielectric layer; and an aluminum layer compliantly deposited on the top dielectric layer and in the at least one opening, wherein, when viewed from above, the at least one opening has a regular n-gonal pattern (n is greater than or equal to 6), a circular pattern, or an elliptical pattern.

[0006] According to an embodiment of the present invention, the aluminum layer is in direct contact with the top metal layer.

[0007] According to an embodiment of the present invention, the aluminum layer conformally covers the sidewall of the at least one opening and the bottom surface of the at least one opening, thereby forming a recessed area above the at least one opening.

[0008] According to an embodiment of the present invention, the top surface of the top metal layer of the at least one opening portion is exposed.

[0009] According to an embodiment of the present invention, the aluminum layer is in direct contact with the top surface of the top metal layer through the at least one opening.

[0010] According to an embodiment of the present invention, the semiconductor structure further includes: a passivation layer conformally covering the aluminum layer and the recessed region above the at least one opening, wherein the angle between the sidewall and the top surface of the passivation layer in the recessed region is greater than or equal to 80 degrees.

[0011] According to an embodiment of the present invention, the passivation layer comprises a silicon oxide layer or a silica phosphate glass layer.

[0012] According to an embodiment of the present invention, the passivation layer further comprises a silicon nitride layer located on the silicon oxide layer or the silica phosphate glass layer.

[0013] According to an embodiment of the present invention, the top metal layer comprises tungsten.

[0014] According to an embodiment of the present invention, the top metal layer comprises copper.

[0015] In another aspect, the present invention provides a semiconductor structure comprising: a substrate; a first top metal layer disposed on the substrate; a second top metal layer disposed on the substrate, wherein the second top metal layer is spaced apart from the first top metal layer; a top dielectric layer disposed on the first top metal layer, the second top metal layer and the substrate; at least one first opening located in the top dielectric layer; at least one second opening located in the top dielectric layer; a first aluminum layer conformally deposited on the top dielectric layer and in the at least one first opening; and a second aluminum layer conformally deposited on the top dielectric layer and in the at least one second opening, wherein, when viewed from above, the at least one first opening or the at least one second opening has a regular n-gonal pattern (n is greater than or equal to 6), a circular pattern or an elliptical pattern.

[0016] According to an embodiment of the present invention, the first aluminum layer is in direct contact with the first top metal layer, and the second aluminum layer is in direct contact with the second top metal layer.

[0017] According to an embodiment of the present invention, the first aluminum layer conformally covers the sidewall of the at least one first opening and the bottom surface of the at least one first opening, thereby forming a first recessed area above the at least one first opening, and the second aluminum layer conformally covers the sidewall of the at least one second opening and the bottom surface of the at least one second opening, thereby forming a second recessed area above the at least one second opening.

[0018] According to an embodiment of the present invention, the at least one first opening and the at least one second opening respectively partially expose the top surface of the first top metal layer and the top surface of the second top metal layer.

[0019] According to an embodiment of the present invention, the first aluminum layer and the second aluminum layer are in direct contact with the top surface of the first top metal layer and the top surface of the second top metal layer through the at least one first opening and the at least one second opening, respectively.

[0020] According to an embodiment of the present invention, the semiconductor structure further includes: a passivation layer conformally covering the first aluminum layer, the second aluminum layer, the first recessed region and the second recessed region, wherein the angle between the sidewall and the top surface of the passivation layer in the first recessed region or the second recessed region is greater than or equal to 80 degrees.

[0021] According to an embodiment of the present invention, the passivation layer comprises a silicon oxide layer or a silica phosphate glass layer.

[0022] According to an embodiment of the present invention, the passivation layer further comprises a silicon nitride layer located on the silicon oxide layer or the silica phosphate glass layer.

[0023] According to an embodiment of the present invention, the first top metal layer and the second top metal layer comprise tungsten.

[0024] According to an embodiment of the present invention, the first top metal layer and the second top metal layer comprise copper.

Implementation Method

[0025] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0026] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting, but rather the embodiments included therein will be defined by the appended claims.

[0027] Please refer to Figures 1 and 2, wherein Figure 1 is a top-view perspective view of a semiconductor structure according to an embodiment of the present invention, and Figure 2 is a cross-sectional view along the tangent line I-I' shown in Figure 1. As shown in Figures 1 and 2, the semiconductor structure 1 includes a substrate 100, such as a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, at least one inter-metal dielectric layer 110, such as a low dielectric constant material layer or an ultra-low dielectric constant material layer, and at least one lower metal layer DL are disposed in the at least one inter-metal dielectric layer 110. According to an embodiment of the present invention, the at least one lower metal layer DL is, for example, an embedded copper metal layer, but is not limited thereto.

[0028] According to an embodiment of the present invention, a first top metal layer TM1 and a second top metal layer TM2 are further disposed on the substrate 100, wherein the second top metal layer TM2 is spaced apart from the first top metal layer TM1. According to an embodiment of the present invention, the first top metal layer TM1 and the second top metal layer TM2 are, for example, embedded copper metal layers, but are not limited thereto. According to an embodiment of the present invention, the first top metal layer TM1 and the second top metal layer TM2 are the uppermost copper metal layers in the copper metal interconnect structure of the semiconductor structure 1. According to other embodiments of the present invention, the first top metal layer TM1 and the second top metal layer TM2 may contain tungsten.

[0029] According to an embodiment of the present invention, a top dielectric layer 120, such as a silicon oxide layer or a silicon nitride layer, is covered on the first top metal layer TM1 and the second top metal layer TM2, but is not limited thereto. As can be seen from Figure 2, the first top metal layer TM1 is electrically connected to at least one lower metal layer DL via a dielectric plug TV.

[0030] According to an embodiment of the present invention, at least one first opening OP1 and at least one second opening OP2 are formed in the top dielectric layer 120, wherein the at least one first opening OP1 and at least one second opening OP2 are respectively located directly above the first top metal layer TM1 and the second top metal layer TM2, and respectively expose a portion of the top surface of the first top metal layer TM1 and a portion of the top surface of the second top metal layer TM2. According to an embodiment of the present invention, when viewed from above, as shown in Figure 1, the at least one first opening OP1 or the at least one second opening OP2 may have, for example, a regular octagonal pattern, but is not limited thereto. In other embodiments, when viewed from above, the at least one first opening OP1 or the at least one second opening OP2 may have a regular n-gonal pattern (n is greater than or equal to 6), a circular pattern, or an elliptical pattern.

[0031] According to an embodiment of the present invention, a first aluminum layer AL1 is disposed on the top dielectric layer 120, conformally deposited on the top dielectric layer 120 and in at least one first opening OP1; and a second aluminum layer AL2 is conformally deposited on the top dielectric layer 120 and in at least one second opening OP2. According to an embodiment of the present invention, the first aluminum layer AL1 and the second aluminum layer AL2 are spaced apart from each other. According to an embodiment of the present invention, the first aluminum layer AL1 is in direct contact with the top surface of the first top metal layer TM1 via at least one first opening OP1, and the second aluminum layer AL2 is in direct contact with the top surface of the second top metal layer TM2 via at least one second opening OP2.

[0032] According to an embodiment of the present invention, a first aluminum layer AL1 conformally covers the sidewall of at least one first opening OP1 and the bottom surface of at least one first opening OP1, thereby forming a first recessed area R1 above at least one first opening OP1, and a second aluminum layer AL2 conformally covers the sidewall of at least one second opening OP2 and the bottom surface of at least one second opening OP2, thereby forming a second recessed area R2 above at least one second opening OP2.

[0033] According to an embodiment of the present invention, the semiconductor structure 1 further includes a passivation layer PL, which conformally covers a first aluminum layer AL1, a second aluminum layer AL2, a first recessed region R1, and a second recessed region R2. According to an embodiment of the present invention, the passivation layer PL includes a silicon oxide layer P1 or a phosphosilicate glass (PSG) layer. According to an embodiment of the present invention, the passivation layer PL may further include a silicon nitride layer P2 located on the silicon oxide layer P1. As shown in the partial enlarged view in Figure 2, the angle Ɵ between the sidewall S1 and the top surface S2 of the passivation layer PL in the first recessed region R1 or the second recessed region R2 is greater than or equal to 80 degrees. Therefore, the passivation layer PL has better step coverage in at least one first opening OP1 or at least one second opening OP2, which can avoid the generation of cracks in the subsequent wet etching process. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0034] Figure 1 is a top perspective view of a semiconductor structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view along the tangent line I-I' shown in Figure 1.

Claims

1. A semiconductor structure comprising: a substrate; a top metal layer disposed on the substrate; a top dielectric layer disposed on the substrate and the top metal layer; at least one opening disposed in the top dielectric layer; and an aluminum layer compliantly deposited on the top dielectric layer and in the at least one opening, wherein, When viewed from above, the at least one opening has a regular n-gonal pattern (n is greater than or equal to 6), a circular pattern, or an elliptical pattern, wherein the aluminum layer conformally covers the sidewalls of the at least one opening and the bottom surface of the at least one opening, thereby forming a recessed area above the at least one opening.

2. The semiconductor structure as described in claim 1, wherein, The aluminum layer is in direct contact with the top metal layer.

3. The semiconductor structure as described in claim 1, wherein, The top surface of the top metal layer is exposed by at least one opening.

4. The semiconductor structure as described in claim 3, wherein, The aluminum layer is in direct contact with the top surface of the top metal layer through the at least one opening.

5. The semiconductor structure as described in claim 1, wherein, It also includes: a passivation layer conformally covering the aluminum layer and the recessed area above the at least one opening, wherein the angle between the sidewall of the passivation layer and the top surface within the recessed area is greater than or equal to 80 degrees.

6. The semiconductor structure as described in claim 5, wherein, The passivation layer comprises a silicon oxide layer or a silica phosphate glass layer.

7. The semiconductor structure as described in claim 6, wherein, The passivation layer further comprises a silicon nitride layer located on the silicon oxide layer or the silica phosphate glass layer.

8. The semiconductor structure as claimed in claim 1, wherein, The top metal layer contains tungsten.

9. The semiconductor structure as claimed in claim 1, wherein, The top metal layer contains copper.

10. A semiconductor structure comprising: a substrate; a first top metal layer disposed on the substrate; and a second top metal layer disposed on the substrate, wherein, The second top metal layer is spaced apart from the first top metal layer; a top dielectric layer is disposed on the first top metal layer, the second top metal layer and the substrate; at least one first opening is located in the top dielectric layer; at least one second opening is located in the top dielectric layer; a first aluminum layer is conformally deposited on the top dielectric layer and in the at least one first opening; A second aluminum layer is conformally deposited on the top dielectric layer and in the at least one second opening, wherein, when viewed from above, the at least one first opening or the at least one second opening has a regular n-gonal pattern (n greater than or equal to 6), a circular pattern, or an elliptical pattern, wherein the first aluminum layer conformally covers the sidewalls and bottom surface of the at least one first opening, thereby forming a first recessed area above the at least one first opening, and the second aluminum layer conformally covers the sidewalls and bottom surface of the at least one second opening, thereby forming a second recessed area above the at least one second opening.

11. The semiconductor structure as described in claim 10, wherein, The first aluminum layer is in direct contact with the first top metal layer, and the second aluminum layer is in direct contact with the second top metal layer.

12. The semiconductor structure as claimed in claim 10, wherein, The at least one first opening and the at least one second opening respectively partially expose the top surface of the first top metal layer and the top surface of the second top metal layer.

13. The semiconductor structure as described in claim 12, wherein, The first aluminum layer and the second aluminum layer are in direct contact with the top surfaces of the first top metal layer and the second top metal layer, respectively, through the at least one first opening and the at least one second opening.

14. The semiconductor structure as claimed in claim 10, wherein, It also includes: a passivation layer conformally covering the first aluminum layer, the second aluminum layer, the first recessed region, and the second recessed region, wherein the angle between the sidewall of the passivation layer and the top surface in the first recessed region or the second recessed region is greater than or equal to 80 degrees.

15. The semiconductor structure as described in claim 14, wherein, The passivation layer comprises a silicon oxide layer or a silica phosphate glass layer.

16. The semiconductor structure as claimed in claim 15, wherein, The passivation layer further comprises a silicon nitride layer located on the silicon oxide layer or the silica phosphate glass layer.

17. The semiconductor structure as claimed in claim 10, wherein, The first top metal layer and the second top metal layer contain tungsten.

18. The semiconductor structure as claimed in claim 10, wherein, The first top metal layer and the second top metal layer contain copper.

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