Semiconductor device

Abstract

A semiconductor device includes a substrate, a first well region, a second well region, a third well region, a source contact region, a drain contact region, a gate electrode and a buried layer. The first well region has a first conductivity type and is disposed in the substrate. The second well region has the first conductivity type, is disposed in the substrate, and surrounds the first well region. The third well region has a second conductivity type, is disposed in the substrate and located between the first well region and the second well region, and surrounds the first well region. The source contact region is disposed in the second well region, the drain contact region is disposed in the first well region, and the gate electrode is disposed directly above the third well region. The buried layer has the second conductivity type, is disposed in the substrate, and extends laterally from directly below the third well region to directly below the second well region.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device suitable for switching circuits, and more particularly to a semiconductor device incorporating a double-diffused metal-oxide-semiconductor (DMOS) transistor around a level shifter region. [Previous Technology]

[0002] Switching circuits (or bridge circuits) typically include high-side (or upper bridge) components, low-side (or lower bridge) components, a boost converter, a level shift circuit, a high-side drive circuit, a low-side drive circuit, and control logic. The high-side and low-side components are connected in series and alternately turned on and off. In the boost converter of a switching circuit, a bootstrap diode is required between the high-side and low-side voltages. When the high-side circuit is on, the bootstrap diode operates under reverse bias to prevent high-voltage signals from damaging the low-side circuit; when the high-side circuit is off, the bootstrap diode operates under forward bias to charge the capacitors in the boost converter using the low-side voltage, thereby maintaining the high-side voltage at a certain level. However, in switching circuits, current bootstrap diode architectures cannot meet the various requirements of integrated circuits. [Summary of the Invention]

[0003] In view of this, the present disclosure proposes a semiconductor device suitable for switching circuits, in which a double-diffused metal-oxygen semiconductor (DMOS) transistor is incorporated around the level shifter region to replace the bootstrap diode architecture in the boost device, and a buried layer is provided below the channel region and source well region of the DMOS transistor to reduce the parasitic NPN bipolar transistor effect, thereby avoiding or reducing substrate leakage current, while not affecting the various electrical performances of the semiconductor device.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including a substrate, a first well region, a second well region, a third well region, a source contact region, a drain contact region, a gate, and a buried layer. The first well region has a first conductivity type and is disposed within the substrate. The second well region has a first conductivity type and is disposed within the substrate, surrounding the first well region. The third well region has a second conductivity type and is disposed within the substrate, located between the first and second well regions, and surrounding the first well region. The source contact region is disposed within the second well region, the drain contact region is disposed within the first well region, and the gate is disposed directly above the third well region. The buried layer has a second conductivity type and is disposed within the substrate, extending laterally from directly below the third well region to directly below the second well region.

[0005] In order to make the features of this disclosure clear and easy to understand, embodiments are provided below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0006] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature is formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0007] Furthermore, regarding the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "down," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the diagram. In addition to the orientation shown in the diagram, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0008] Although this disclosure uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0009] The terms "about" or "substantially" used in this disclosure generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" may be implied even without specific description of "about" or "substantially".

[0010] The terms “coupled,” “coupled,” and “electrically connected” used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0011] Although the invention disclosed herein is described below by way of specific embodiments, the inventive principles of this invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0012] This disclosure relates to a semiconductor device incorporating a double-diffused metal-oxide-semiconductor (DMOS) transistor in the periphery of the level shifter region. It is suitable for switching circuits. The DMOS transistor can replace the bootstrap diode architecture in a boost converter. A buried layer is disposed beneath the channel region and the well region of the source of the DMOS transistor. This buried layer reduces the parasitic NPN bipolar transistor effect, thereby avoiding or reducing substrate leakage current without affecting the various electrical performance characteristics of the semiconductor device, thus improving the utilization of the semiconductor device in integrated circuits. Furthermore, the fabrication of the DMOS transistor including the buried layer can be integrated with the process of the level shifter region, thus eliminating the need for additional photomasks and process steps, thereby saving on the manufacturing cost of the semiconductor device.

[0013] Figure 1 is a top view of a semiconductor device 100 according to an embodiment of the present disclosure, showing the planar arrangement of a buried layer 120 and some components. The buried layer 120 has a rectangular pattern. For the sake of simplicity and clarity, Figure 1 shows the substrate 101, the level shifting element region 108, and the first well region 111, the third well region 113, the buried layer 120, the drain contact region 121, the source contact region 122, and the base (bulk) contact region 124 of the DMOS transistor surrounding the level shifting element region 108. Other components of the semiconductor device 100 (not shown) will be shown and described in Figures 2 and 3.

[0014] Referring to Figure 1, a first well region 111 is disposed in a substrate 101, and a drain contact region 121 is disposed on the first well region 111. A level shifting element region 108 is disposed in the substrate 101. Viewed from a top angle, a buried layer 120 surrounds the level shifting element region 108 and the first well region 111. Furthermore, a third well region 113 is disposed on the buried layer 120, and a source contact region 122 is located above the buried layer 120. The third well region 113 serves as the channel region for the DMOS transistor and is located between the drain contact region 121 and the source contact region 122. In this embodiment, a base contact region 124 is also located above the buried layer 120, surrounding the source contact region 122, and the vertical projection area of ​​the buried layer 120 extends beyond the base contact region 124. In one embodiment, the outer surface 120S2 of the buried layer 120 may be vertically aligned with the outer surface 114S of the fourth well region (not shown) where the base contact region 124 is located. Additionally, the level shifting element region 108 may include a transistor 107 located on one side, and the buried layer 120 may continuously or discontinuously surround the level shifting element region 108, but not necessarily the transistor 107. In one embodiment, as shown in Figure 1, the buried layer 120 may be a C-shaped annular region continuously surrounding the level shifting element region 108. In another embodiment, the buried layer 120 may be composed of multiple separate blocks, thus discontinuously surrounding the level shifting element region 108. To clearly show some features of the semiconductor device 100, the dimensions of some components other than the level shifting element region 108 are shown enlarged in Figure 1; in reality, the dimensions of each component can be adjusted according to layout requirements.

[0015] Figure 2 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure, which is drawn along the tangent line AA of the cross-section in Figure 1, showing the DMOS transistors surrounding the level shifting element region 108. Referring to Figure 2, the semiconductor device 100 includes a substrate 101. In one embodiment, the substrate 101 is formed, for example, by stacking a P-type epitaxial layer 101-2 on a P-type substrate 101-1. Furthermore, the semiconductor device 100 includes a first well region 111 disposed within the substrate 101. The first well region 111 has a first conductivity type, for example, formed by stacking high-voltage N-type well regions (HVNW) on high-voltage N-type deep well regions (DHVNW). A drain contact region 121 is disposed within the first well region 111. The drain contact region 121 has a first conductivity type, for example, an N-type heavily doped region (N+). A second well region 112 is disposed within the substrate 101 and surrounds the first well region 111. The second well region 112 has a first conductivity type, such as an N-type well region (NW), and the bottom surface of the second well region 112 is higher than the bottom surface of the first well region 111. A source contact region 122 is disposed within the second well region 112 and has a first conductivity type, such as an N-type heavily doped region (N+).

[0016] A third well region 113 is disposed within the substrate 101, located between the first well region 111 and the second well region 112, and surrounding the first well region 111. The third well region 113 is laterally separated from both the first well region 111 and the second well region 112. The third well region 113 has a second conductivity type, such as a P-type well region (PW), and a heavily doped P-type region (P+) 123 is disposed on the third well region 113. A fourth well region 114 is disposed within the substrate 101, surrounding and adjacent to the second well region 112. The bottom surface of the fourth well region 114 and the bottom surface of the second well region 112 may be at the same horizontal height. The fourth well region 114 has a second conductivity type, such as a P-type well region (PW), and a bulk contact region 124 is disposed within the fourth well region 114. The bulk contact region 124 also has a second conductivity type, such as a heavily doped P-type region (P+).

[0017] Multiple isolation regions 130, such as field oxide (FOX) or shallow trench isolation (STI) structures, are disposed on the substrate 101 and located between the substrate contact region 124, the source contact region 122, the heavily doped P-type region 123, and the drain contact region 121. A gate 133 is disposed directly above the third well region 113, and the gate 133 is composed, for example, polysilicon. The third well region 113 serves as the channel region of the DMOS transistor, and the channel region length Lch is the length of the third well region 113 in the direction (X-axis direction) from the first well region 111 to the second well region 122. A gate dielectric layer 131 is disposed below the gate 133 and located between the gate 133 and the heavily doped P-type region (P+) 123. Additionally, a P-type doped top layer (PTOP) 117 can be disposed in the first well region 111, directly below the isolation region 130 between the gate 133 and the drain contact region 121. The P-type doped top layer 117 can reduce the surface electric field. A field plate 135 is disposed on the isolation region 130 directly above the P-type doped top layer 117 and adjacent to the drain contact region 121. The field plate 135 can disperse the electric field. The field plate 135 is composed, for example, of polycrystalline silicon and can be formed simultaneously with the gate 133 via deposition and patterning processes. Furthermore, a portion of the gate 133 can also extend laterally onto the isolation region 130 to serve as another field plate. A metal layer 140 is disposed on the substrate 101. The metal layer 140 may include a substrate electrode 140B, a source electrode 140S, a gate electrode 140G, and a drain electrode 140D, which are electrically connected to the substrate contact region 124, the source contact region 122, the gate electrode 133, the field plate 135, and the drain contact region 121, respectively, vias 139. The vias 139, the gate electrode 133, and the field plate 135 may be located within an interlayer dielectric layer (not shown), and the metal layer 140 may be formed on the interlayer dielectric layer.

[0018] According to some embodiments of this disclosure, the semiconductor device 100 further includes a buried layer 120 disposed within a substrate 101, extending at least laterally from directly beneath a third well region 113 along an XY plane to directly beneath a second well region 112, and the inner side surface 120S1 of the buried layer 120 contacts the side surface of the first well region 111. The buried layer 120 has a second conductivity type, such as a P-type buried layer (PBL), and the doping concentration of the buried layer 120 is higher than the doping concentration of the substrate 101 and lower than the doping concentration of the third well region 113. In some embodiments, the doping concentration of the buried layer 120 is, for example, from about 1E17 cm⁻³ to about 1E18 cm⁻³. In this embodiment, the buried layer 120 further extends laterally from directly beneath the second well region 112 to directly beneath a fourth well region 114. Viewed from a top-down angle, the outer surface 120S2 of the buried layer 120 can be vertically aligned with the outer surface 114S of the fourth well area 114, and the vertical projected area of ​​the buried layer 120 can be greater than the sum of the vertical projected areas of the second well area 112, the third well area 113, and the fourth well area 114. In one embodiment, the top surface of the buried layer 120 can contact the bottom surface of the second well area 112, the bottom surface of the third well area 113, and the bottom surface of the fourth well area 114. In another embodiment, the top surface of the buried layer 120 can contact the bottom surface of the third well area 113, and is slightly lower than the bottom surfaces of the second well area 112 and the fourth well area 114. Furthermore, the bottom surface of the buried layer 120 is higher than the bottom surface of the first well area 111.

[0019] In the semiconductor device 100, parasitic NPN bipolar transistors are generated in the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW). When the concentration of P-type dopant at the bottom of the parasitic NPN bipolar transistor is higher, and / or the width of the bottom P-type doped region in the XY plane is larger, the β current gain of the parasitic NPN bipolar transistor can be reduced. The lower the β current gain, the smaller the current amplification factor through the substrate 101, thereby avoiding or reducing substrate leakage current. According to some embodiments of this disclosure, since the doping concentration of the buried layer 120 is higher than that of the substrate 101, that is, the doping concentration of the buried layer 120 is higher than that of the P-type epitaxial layer 101-2 and also higher than that of the P-type substrate 101-1, and the buried layer 120 extends at least laterally from directly below the third well region 113 to directly below the second well region 112. Compared to a comparative example where the third well region 113, the second well region 112, and the fourth well region 114 do not have a buried layer 120 directly below them, resulting in a low-doped P-type epitaxial layer 101-2 at the bottom of the parasitic NPN bipolar transistor, the embodiment disclosed herein effectively reduces the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW), thereby reducing the β current gain value. Even under operating conditions with increased current, it can still effectively avoid or reduce substrate leakage current. Furthermore, the buried layer 120 does not affect various electrical performance characteristics of the semiconductor device 100, such as the electrical performance in terms of threshold voltage (Vt), drive current (Ion), saturation current (Isat), off-state breakdown voltage (BVoff), and NW junction breakdown voltage (NW junction BV).

[0020] Figure 3 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. It is drawn along the tangent line B-B' of the cross-section in Figure 1, showing a level shifting element region 108, including a transistor 107 and a high-side element 109. In one embodiment, the transistor 107 includes a first high-voltage well region 103, a fifth well region 105, and a P-type buried layer (PBL) 110 disposed in a substrate 101. The first high-voltage well region 103 may be formed, for example, by stacking high-voltage N-type well regions (HVNW) on high-voltage N-type deep well regions (DHVNW). The fifth well region 105 may be, for example, a P-type well region (PW). The P-type buried layer 110 is located directly below the fifth well region 105, and both the fifth well region 105 and the P-type buried layer 110 are laterally separated from the first high-voltage well region 103. A drain contact region 151 is disposed within a first high-voltage well region 103, and a source contact region 152 and a substrate contact region 154 are disposed within a fifth well region 105. Both the drain contact region 151 and the source contact region 152 are, for example, heavily N-type doped regions (N+), and the substrate contact region 154 is, for example, heavily P-type doped regions (P+). A gate 153 is disposed on a substrate 101, and a gate dielectric layer 131 is disposed between the gate 153 and the substrate 101. An isolation region 130 is disposed between the gate 153 and the drain contact region 151, and a P-type doped top layer 117 is disposed directly below this isolation region 130 to reduce the surface electric field.

[0021] Referring again to Figure 3, the high-side element 109 includes a second high-pressure well region 104, a sixth well region 106, and a P-type buried layer 110 disposed within the substrate 101. The second high-pressure well region 104 may be formed, for example, by stacking high-pressure N-type well regions (HVNW) on high-pressure N-type deep well regions (DHVNW). The sixth well region 106 may be, for example, a P-type well region (PW). The P-type buried layer 110 is located directly below the sixth well region 106, and both the sixth well region 106 and the P-type buried layer 110 are laterally separated from the second high-pressure well region 104. Furthermore, a P-type well region 116 is disposed between the first high-pressure well region 103 of the transistor 107 and the second high-pressure well region 104 of the high-side element 109 as an isolation ring to isolate the transistor 107 and the high-side element 109. A field plate 155 is disposed on the isolation region 130 above the P-type well region 116. An N-type heavily doped region (N+) 162 is disposed within the second high-voltage well region 104, and a P-type heavily doped region (P+) 164 is disposed within the sixth well region 106. A gate 163 is disposed on the substrate 101, and a gate dielectric layer 131 is disposed between the gate 163 and the substrate 101. An isolation region 130 is disposed between the N-type heavily doped region (N+) 162 and the gate 163, and another P-type doped top layer 117 is disposed directly below this isolation region 130 to reduce the surface electric field. A metal layer 140 is disposed on the substrate 101. The metal layer 140 includes a plurality of electrode portions that are laterally separated from each other. These portions are electrically connected to the substrate contact region 154, source contact region 152, gate 153, drain contact region 151 and field plate 155 of the transistor 107 via a plurality of vias 139, and are electrically connected to the N-type heavily doped region 162, gate 163 and P-type heavily doped region 164 of the high-side element 109, respectively.

[0022] The fabrication of the DMOS transistors surrounding the level shifting element region 108 can be integrated with the fabrication process of the level shifting element region 108. The first well region 111 of the DMOS transistor and the first high-voltage well region 103 and the second high-voltage well region 104 of the level shifting element region 108 can be formed simultaneously via the same ion implantation process. The fourth well region 114 of the DMOS transistor and the fifth well region 105 and the sixth well region 106 of the level shifting element region 108 can be formed via the same ion implantation process. The buried layer 120 of the DMOS transistor and the P-type buried layer 110 of the level shifting element region 108 can also be formed via the same ion implantation process. The buried layer 120 and the P-type buried layer 110 have the same conductivity type and doping concentration, and the bottom surfaces of the buried layer 120 and the P-type buried layer 110 can be approximately at the same horizontal level. Furthermore, the ion implantation process for forming the buried layer 120 and the P-type buried layer 110 is performed only after the second well region 112, the third well region 113, and the fourth well region 114 are formed, thereby avoiding any impact on the various electrical performance characteristics of the semiconductor device 100. Other similar components of the DMOS transistor and the level shifting element region 108, such as heavily doped regions, P-type doped top layers, isolation regions, gates, and field plates with the same conductivity type, can also be formed together via the same process steps. Therefore, according to some embodiments disclosed herein, the fabrication of the DMOS transistor, which includes the buried layer 120 and is incorporated around the level shifting element region 108, does not require additional photomasks and process steps, thereby saving on the manufacturing cost of the semiconductor device.

[0023] Figure 4 is a top view of a semiconductor device 100 according to another embodiment of the present disclosure, wherein the buried layer 120 of the DMOS transistor surrounding the level shifting element region 108 has a racetrack-shaped pattern. For clarity, Figure 4 depicts the substrate 101, the level shifting element region 108, and the third well region 113, buried layer 120, drain contact region 121, source contact region 122, and base contact region 124 of the semiconductor device 100. Other components of the semiconductor device 100 will be illustrated in Figure 5. As shown in Figure 4, in one embodiment, the DMOS transistor surrounding the level shifting element region 108 may have a racetrack-shaped pattern, wherein the drain contact region 121, source contact region 122, base contact region 124, third well region 113, and buried layer 120 surround the level shifting element region 108 and have a racetrack-shaped planar configuration. To clearly show some features of the semiconductor device 100, the dimensions of some components other than the level shifting element region 108 are drawn enlarged in Figure 4. In reality, the size of the level shifting element region 108 can be larger. In this embodiment, viewed from a top angle, the outer surface 120S2 of the buried layer 120 is within the base contact region 124, and the third well region 113 corresponds to the racetrack-shaped pattern of the buried layer 120 and is disposed directly above the buried layer 120.

[0024] Figure 5 is a cross-sectional schematic diagram of a semiconductor device 100 according to another embodiment of the present disclosure. It is drawn along the tangent CC of the cross section in Figure 4, showing the DMOS transistors merging around the level shifting element region 108. In this embodiment, the buried layer 120 extends laterally from directly below the third well region 113 to directly below the second well region 112. The outer surface 120S2 of the buried layer 120 can be vertically aligned with the outer surface 112S of the second well region 112, and the buried layer 120 does not extend directly below the fourth well region 114. The vertical projected area of ​​the buried layer 120 can be greater than the sum of the vertical projected areas of the second well region 112 and the third well region 113. Details of other components of the semiconductor device 100 in Figure 5 can be found in the relevant description of the semiconductor device 100 in Figure 2 above, and will not be repeated here.

[0025] Furthermore, when the adjacent components of the semiconductor device 100 do not primarily use N-type well regions, for example, when the adjacent components are not PMOS transistors, as shown in Figure 5, the P-type buried layer 120 does not need to extend directly below the fourth well region 114. When the adjacent components of the semiconductor device 100 primarily use N-type well regions, for example, when the adjacent components are PMOS transistors, as shown in Figure 2, the P-type buried layer 120 needs to extend directly below the fourth well region 114 to reduce the parasitic NPN bipolar transistor effect between the second well region 112 (NW), the fourth well region 114 (PW) of the semiconductor device 100 and the N-type well regions of the adjacent components.

[0026] Figure 6 is a schematic cross-sectional view of a semiconductor device 100 according to another embodiment of the present disclosure, illustrating a DMOS transistor incorporated around a level shifting element region. In this embodiment, the buried layer 120 extends laterally from directly below the third well region 113 to directly below the second well region 112, and also laterally to a portion directly below the fourth well region 114, for example, the buried layer 120 may extend directly below the base contact region 124. Viewed from a top angle, the outer surface 120S2 of the buried layer 120 is located between the outer surface 112S of the second well region 112 and the outer surface 114S of the fourth well region 114. The buried layer 120 of the embodiment in Figure 6 may also reduce the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW), thereby reducing the β current gain value to avoid or reduce substrate leakage current. For details of the other components of the semiconductor device 100 in Figure 6, please refer to the relevant description of the semiconductor device 100 in Figure 2 above, which will not be repeated here.

[0027] Figure 7 is a top view of a semiconductor device 100 according to another embodiment of the present disclosure, wherein the buried layer 120 of the DMOS transistor surrounding the level shifting element region 108 has a finger-shaped pattern. For the sake of simplicity and clarity, Figure 7 shows the substrate 101, the level shifting element region 108, and the third well region 113, buried layer 120, drain contact region 121, source contact region 122, and base contact region 124 of the semiconductor device 100. Other components of the semiconductor device 100 (not shown) can be referred to the relevant description in Figure 2 above. As shown in Figure 7, in one embodiment, the DMOS transistor surrounding the level shifting element region 108 may have a finger-shaped pattern, wherein the drain contact region 121, source contact region 122, base contact region 124, third well region 113, and buried layer 120 all surround the level shifting element region 108 and all have a finger-shaped planar arrangement. Viewed from above, the third well region 113 corresponds to the finger-shaped pattern of the buried layer 120 and is positioned directly above the buried layer 120. To clearly show some features of the semiconductor device 100, the dimensions of some components other than the level shifting element region 108 are enlarged in Figure 7. The relative size ratio of the level shifting element region 108 and its surrounding DMOS transistors can be adjusted according to actual needs. In the embodiment shown in Figure 7, Figure 6 can also be consulted; the outer surface 120S2 of the buried layer 120 can be substantially vertically aligned with the base contact region 124.

[0028] According to some embodiments of this disclosure, the DMOS transistor of the semiconductor device incorporated around the level shifting element region includes a buried layer, and the buried layer (PBL) of the second conductivity type extends laterally from directly below the third well region (PW) of the second conductivity type in the channel region to directly below the second well region (NW) of the first conductivity type in the source region. The buried layer (PBL) can reduce the parasitic NPN bipolar transistor effect generated by the first well region 111 (NW), the third well region 113 (PW), and the second well region 112 (NW) of the first conductivity type, thereby reducing the β current gain value and thus avoiding or reducing the substrate leakage current of the semiconductor device. At the same time, the various electrical performance characteristics of the semiconductor device are not affected, and the utilization of the semiconductor device in integrated circuits can be improved.

[0029] Furthermore, according to some embodiments disclosed herein, the fabrication of the DMOS transistor including the buried layer can be integrated with the process of the level shifting element region. Therefore, no additional photomask and process steps are required, thereby saving the manufacturing cost of the semiconductor device. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0030] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed textual descriptions while reading this disclosure. The specific embodiments described herein, along with the corresponding drawings, are explained in detail to illustrate the working principles of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale, and the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 is a top view of a semiconductor device according to an embodiment of this disclosure, showing the planar arrangement of the buried layer and some components. Figure 2 is a cross-sectional view of a semiconductor device according to an embodiment of this disclosure, drawn along the tangent line AA of Figure 1. Figure 3 is a cross-sectional view of a semiconductor device according to an embodiment of this disclosure, drawn along the tangent line B-B' of Figure 1. Figure 4 is a top view of a semiconductor device according to another embodiment of this disclosure, showing the planar arrangement of the buried layer with a racetrack-shaped pattern and some components. Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure, drawn along the tangent line CC of the section in Figure 4. Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to yet another embodiment of the present disclosure. Figure 7 is a top view schematic diagram of a semiconductor device according to yet another embodiment of the present disclosure, showing a planar arrangement of a buried layer with a finger-shaped pattern and some components.

Claims

1. A semiconductor device, comprising: One base; A first well zone, having a first conductivity type, is disposed within the substrate; A second well region, having the first conductivity type, is disposed within the substrate and surrounds the first well region; a third well region, having the second conductivity type, is disposed within the substrate, located between the first and second well regions, surrounds the first well region, and is entirely laterally separated from the first well region; a source contact region is disposed within the second well region; a drain contact region is disposed within the first well region; and a gate is disposed directly above the third well region. And a buried layer having the second conductivity type, disposed within the substrate, extending laterally from directly below the third well area to directly below the second well area.

2. The semiconductor device as claimed in claim 1, wherein the vertical projected area of ​​the buried layer is greater than the sum of the vertical projected areas of the second well region and the third well region.

3. The semiconductor device as claimed in claim 1, wherein the top surface of the buried layer contacts the bottom surface of the second well region and the bottom surface of the third well region.

4. The semiconductor device as claimed in claim 1, wherein an outer side of the buried layer is perpendicularly aligned with an outer side of the second well region.

5. The semiconductor device as described in claim 1, further comprising: A fourth well region, having the second conductivity type, is disposed within the substrate, surrounding and adjacent to the second well region; And a base contact area is provided in the fourth well area, wherein the buried layer extends laterally from directly below the second well area to directly below the fourth well area.

6. The semiconductor device as claimed in claim 5, wherein an outer side of the buried layer is perpendicularly aligned with an outer side of the fourth well region.

7. The semiconductor device as claimed in claim 5, wherein, viewed from a top view, an outer side of the buried layer is located between an outer side of the second well region and an outer side of the fourth well region.

8. The semiconductor device as claimed in claim 5, wherein the vertical projected area of ​​the buried layer is greater than the sum of the vertical projected areas of the second well region, the third well region, and the fourth well region.

9. The semiconductor device as claimed in claim 5, wherein the top surface of the buried layer contacts the bottom surface of the second well region, the bottom surface of the third well region, and the bottom surface of the fourth well region.

10. The semiconductor device as claimed in claim 1, wherein an inner side of the buried layer contacts a side of the first well region.

11. The semiconductor device as claimed in claim 1, wherein the bottom surface of the buried layer is higher than the bottom surface of the first well region.

12. The semiconductor device as claimed in claim 1, wherein the third well region is laterally separated from the second well region.

13. The semiconductor device as claimed in claim 1, wherein the substrate has the second conductivity type and the buried layer has a higher doping concentration than the substrate.

14. The semiconductor device as claimed in claim 1, wherein the doping concentration of the buried layer is lower than the doping concentration of the third well region.

15. The semiconductor device as claimed in claim 1, further comprising a quasi-shifting element region disposed in the substrate, wherein, viewed from a top view, the buried layer surrounds the quasi-shifting element region.

16. The semiconductor device as claimed in claim 15, wherein, viewed from a top view, the buried layer includes a racetrack-shaped pattern or a finger-shaped pattern.

17. The semiconductor device as claimed in claim 16, wherein, viewed from a top-down angle, the third well area corresponds to the runway-shaped pattern or the finger-shaped pattern and is disposed directly above the buried layer.

18. The semiconductor device as claimed in claim 15, wherein, viewed from a top view, the buried layer continuously surrounds the level shifting element region.

19. The semiconductor device as claimed in claim 15, wherein, viewed from a top view, the buried layer discontinuously surrounds the level shifting element region.

20. The semiconductor device as claimed in claim 15, wherein the level shifting element region includes another buried layer having the second conductivity type, disposed within the substrate, the buried layer and the other buried layer having the same doping concentration, and the bottom surfaces of the buried layer and the other buried layer being at the same horizontal level.

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