Three-dimensional semiconductor integrated circuit with inter-die connections and method for manufacturing the same

Abstract

There is provided a 3D semiconductor integrated circuit including a system-on-chip (SoC) wafer and a companion wafer. The SoC wafer includes multiple SoC dies. The companion wafer includes multiple companion dies with inter-die connections between adjacent companion dies. The SoC wafer is bonded onto the companion wafer to cause the multiple SoC dies to communicate to adjacent SoC dies via the inter-die connections on the companion wafer.

Claims

1. A three-dimensional semiconductor integrated circuit, comprising: two system-on-a-chip (SoCs) adjacent to each other, each of the two SoCs including a first multi-level wiring layer; and two companion chips adjacent to each other with at least one inter-chip interconnect therebetween, each of the two companion chips including a second multi-level wiring layer for the at least one inter-chip interconnect, wherein... Each of the two system-on-a-chip (SoCs) is coupled to each of the two accompanying chips via a hybrid bonding, such that one of the two SoCs communicates with the other of the two SoCs via the hybrid bonding and the at least one inter-chip connection, and the one of the two SoCs is configured to communicate with the other of the two SoCs via the first and second rewiring layers.

2. The three-dimensional semiconductor integrated circuit as described in claim 1, wherein, Each of the two system-on-a-chip includes a plurality of first bonding pads, each of the two accompanying chips includes a plurality of second bonding pads, and one of the two system-on-a-chips is configured to communicate with the other of the two system-on-a-chips without through the first bonding pads or the second bonding pads.

3. The three-dimensional semiconductor integrated circuit as described in claim 1, wherein, The second rewiring layer of the two accompanying wafers is not connected to any circuitry in the two accompanying wafers.

4. The three-dimensional semiconductor integrated circuit as described in claim 1, wherein, The first rewiring layer of the two system-on-a-chip is connected to the transmitting and receiving circuits in the two system-on-a-chip.

5. The three-dimensional semiconductor integrated circuit as described in claim 1, wherein, The first rewiring layer is covered by a first non-conductive layer having a first bonding portion, the second rewiring layer is covered by a second non-conductive layer having a second bonding portion, and the first bonding portion and the second bonding portion are aligned to serve as longitudinal vias so that the first rewiring layer and the second rewiring layer are electrically coupled.

6. The three-dimensional semiconductor integrated circuit as described in claim 1, wherein, The first wiring layer includes at least one conductor perpendicular to the edge of each system wafer, and the second wiring layer includes at least one conductor extending perpendicularly from the edge of each accompanying wafer.

7. A three-dimensional semiconductor integrated circuit, comprising: a system monolithic wafer including a plurality of system monolithic wafers, the system monolithic wafer further including a first multi-level wiring layer formed on the system monolithic wafers, the first multi-level wiring layer including a first bonding portion; and a companion wafer including a plurality of companion wafers with inter-wafer connections between the companion wafers, the companion wafer further including a second multi-level wiring layer formed on the companion wafers, the second multi-level wiring layer including a second bonding portion, wherein... The accompanying wafer is bonded to the system single-chip wafer so that adjacent system single chips on the system single-chip wafer are electrically coupled to each other through the inter-chip interconnect on the accompanying wafer, and the first bonding portion and the second bonding portion are aligned so that the first redistribution layer and the second redistribution layer are electrically coupled.

8. The three-dimensional semiconductor integrated circuit as described in claim 7, wherein, The inter-chip connections are configured perpendicular to the edges of the accompanying chips.

9. The three-dimensional semiconductor integrated circuit as described in claim 7, wherein, Each accompanying chip contains circuitry, and the interconnects between the chips are not connected to that circuitry.

10. The three-dimensional semiconductor integrated circuit as described in claim 7, wherein, Each system-on-a-chip includes transmit and receive circuitry, and inter-chip connections electrically coupled to the transmit and receive circuitry of the system-on-a-chip.

11. The three-dimensional semiconductor integrated circuit as described in claim 7, wherein, The first bonding portion and the second bonding portion form a longitudinal through-hole that connects to the inter-wafer connection.

12. A method for manufacturing a three-dimensional semiconductor integrated circuit, comprising: providing a system single-chip wafer having one of a plurality of system single-chips, wherein, The system single-chip wafer further includes a first multi-wiring layer formed on the system single-chip, and the first multi-wiring layer includes a first bonding portion; a companion wafer is provided having a plurality of companion wafers and inter-chip connections between the companion wafers, wherein the companion wafer further includes a second multi-wiring layer formed on the companion wafers, and the second multi-wiring layer includes a second bonding portion; and the companion wafer is bonded to the system single-chip wafer such that a system single-chip on the system single-chip wafer is electrically coupled to an adjacent system single-chip on the system single-chip wafer through the inter-chip connections on the companion wafer, wherein the first bonding portion and the second bonding portion are aligned to electrically couple the first multi-wiring layer and the second multi-wiring layer.

13. The manufacturing method as described in claim 12, wherein, The inter-chip connection is not electrically coupled to the circuitry in the accompanying chips.

14. The manufacturing method as described in claim 12, wherein, The step of providing the accompanying wafer further includes: forming a wire perpendicular to the edge of the accompanying wafer as a connection between the wafers, and forming the first bonding portion and the second bonding portion on the wire using a photolithography system.

15. The manufacturing method as described in claim 12 further comprises: cutting the bonded system single-chip wafer and a portion of the accompanying wafer that does not have the inter-chip connection.

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