Semiconductor device and methods of forming the same

Abstract

A semiconductor device includes a high voltage electrostatic discharge (ESD) triggering device that includes a combination of isolation regions (e.g., shallow trench isolation (STI) regions), and resist protective oxide (RPO) structures over doped regions of a substrate. The RPO structures partially overlap STI regions in areas between doped collectors and doped emitters of a high voltage ESD triggering device. The STI regions which are partially overlapped by the RPO structures have widths that allow for unobstructed movement of charge carriers (e.g., holes) from areas between the doped collectors and doped emitters to the doped collectors. As a result, on-resistance (Ron) is reduced in comparison to the Ron for high voltage ESD triggering devices with other isolation region arrangements. Additionally, breakdown voltage is preserved, leading to increased operating efficiency and performance for high voltage ESD triggering devices including the isolation region and RPO structure arrangements.

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