Integrated device and method of manufacturing the same

Abstract

Some embodiments relate to an integrated device, including: a substrate including a first surface and a second surface opposite the first surface; a plurality of photodetectors on the substrate and arranged in a grid pattern; a deep trench isolation (DTI) structure extending between the plurality of photodetectors, the DTI structure including: a first dielectric layer on the first surface and extending towards the second surface, a high work function (WF) layer including a metal or metal oxide and spaced from the substrate by the first dielectric layer, a second dielectric layer, wherein a first portion of the second dielectric layer is spaced from the first dielectric layer by the high WF layer, and an insulative fill extending between inner sidewalls of the second dielectric layer; wherein the high WF layer has a WF greater than

Description

[Technical Field]

[0001] This invention relates to an integrated device for an image sensor and a method for manufacturing the same. [Previous Technology]

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices such as cameras and mobile phones. Image sensors use an array of photodetectors to detect images and transmit signals derived from those images to image processing circuitry. Some image sensors use deep trench isolation (DTI) structures to reduce crosstalk between photodetectors in the array. [Summary of the Invention]

[0003] An integrated device according to the present invention includes: a substrate having a first surface and a second surface opposite to the first surface; a plurality of photodetectors located on the substrate and arranged in a grid pattern; and a deep trench isolation (DTI) structure extending between the plurality of photodetectors, the DTI structure including: a first dielectric layer located on the first surface and extending to the second surface; a high work function (WF) layer comprising a metal or metal oxide and spaced from the substrate by the first dielectric layer; a second dielectric layer, wherein a first portion of the second dielectric layer is spaced from the first dielectric layer by the high work function layer; and an insulating filler extending between the inner sidewalls of the second dielectric layer; wherein the high work function layer has a WF greater than 5 electron volts. Other embodiments relate to an integrated device comprising: a substrate having a first surface and a second surface; a first dielectric layer extending into the substrate from the first surface to the second surface and having internal sidewalls; a high work function (WF) layer lining the internal sidewalls of the first dielectric layer and having internal sidewalls; a second dielectric layer lining the internal sidewalls of the high work function layer; and an insulating filler extending between the internal sidewalls of the second dielectric layer; wherein the high work function layer has a work function greater than 5 electron volts. Other embodiments relate to a method of forming an integrated device, comprising: forming a plurality of photodetectors within a substrate; forming a plurality of transmission transistors on the substrate; forming an interconnect structure on the transmission transistors, the interconnect structure including contacts extending to the transmission transistors; etching a plurality of trenches into the substrate on a first surface of the substrate, the first surface of the substrate facing away from the interconnect structure; depositing a first dielectric layer on the first surface of the substrate and lining the inner sidewalls of the plurality of trenches; forming a high work function (WF) layer comprising a metal or metal oxide on the first surface of the substrate and covering a first portion of the inner sidewalls of the first dielectric layer; and depositing an insulating filler into the plurality of trenches to fill the plurality of trenches.

Implementation Method

[0004] This disclosure provides numerous different embodiments or examples to implement the various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for the purpose of brevity and clarity, but does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0005] Additionally, for ease of explanation, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0006] It should be understood that in this textual description and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements in a single figure or series of figures. In themselves, these terms do not imply any temporal order or structural similarity of the elements and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not illustrated. In some embodiments, the terms "approximately" and / or "about" may be interpreted as meaning ±10% or ±5%, while in other embodiments, the terms "approximately" and / or "about" may be interpreted as meaning within the normal manufacturing tolerances of a given wafer fabrication process.

[0007] The image sensor includes a pixel array having multiple photodetectors and multiple pixel circuits coupled to the photodetectors. The multiple photodetectors are arranged in multiple rows and columns to form a photodetector array. Multiple microlenses are arranged above the photodetector array. A deep trench isolation (DTI) structure is used to separate and isolate the photodetectors, reducing crosstalk and noise from nearby photodetectors.

[0008] In some embodiments, the process of forming the DTI structure can damage the substrate surrounding the DTI structure. Etching processes used to etch trenches in the substrate can damage the inner sidewalls of the trenches (e.g., the substrate region surrounding the trenches). Partial damage manifests as dangling bonds and dislocations in the substrate. The presence of dangling bonds and dislocations in the substrate results in additional eigenstates occupied by electrons, which differ from the eigenstates present in undamaged substrate regions. These additional eigenstates (and therefore also damaged areas of the substrate) introduce noise into the signal received by a photodetector exposed to the damaged areas, leading to degraded image sensor performance. An image sensor capable of reducing or eliminating noise introduced by damaged areas of the substrate surrounding the DTI structure is desirable.

[0009] This disclosure provides a DTI structure including a high work function (WF) layer spaced from a substrate by a first dielectric layer. The high work function layer is or includes a metal oxide or metal with a work function greater than 5 eV. The work function of the high work function layer is greater than the semiconductor work function of the surrounding substrate. The work function difference between the high work function layer and the semiconductor material of the substrate causes a depletion region within the substrate in a region surrounding the DTI structure. The depletion region contains more holes than electrons accumulate in damaged regions of the substrate. Multiple holes increase the probability of electrons in the damaged region recombinating with multiple holes and reduce the probability of electrons from the photodetector interacting with dangling bonds and dislocations in the damaged region. The reduced interaction between electrons and dangling bonds and dislocations in the damaged region reduces the impact of the damaged region on device performance by reducing noise and current leakage caused by interactions between electrons and additional eigenstates in the damaged region.

[0010] Figures 1A, 1B and 1C illustrate cross-sectional views 100a, 100b and 100c of some deep trench isolation (DTI) structure embodiments containing high work function (WF) layers.

[0011] The DTI structure 104 extends into the substrate 102. The substrate 102 surrounds the outer sidewalls of the DTI structure 104 and, in some embodiments, extends beneath the DTI structure 104. The DTI structure 104 includes a first dielectric layer 106, a high work function layer 108, and an insulating filler 110. In some embodiments, the DTI structure 104 further includes a second dielectric layer 112. The first dielectric layer 106 spaces the high work function layer 108 from the substrate 102. In some embodiments, the high work function layer 108 separates the second dielectric layer 112 from the first dielectric layer 106. The insulating filler 110 extends between the inner sidewalls of the first dielectric layer 106, the high work function layer 108, and the second dielectric layer 112.

[0012] The high work function layer 108 is or comprises a material with a work function greater than 5 eV. In some embodiments, the high work function layer 108 is or comprises a transparent metal oxide, such as indium tin oxide (ITO), zinc oxide (ZnO), or the like. In a further embodiment, the transparent metal oxide of the high work function layer 108 is treated (e.g., annealing in an oxygen-rich environment, oxygen plasma surface treatment, etc.) to increase the oxygen content of the material and the first work function of the material, making it equal to or greater than 5 eV. In other embodiments, the high work function layer 108 is or comprises a metal, such as gold (Au), platinum (Pt), or the like.

[0013] The first dielectric layer 106 isolates the high work function layer 108 from the substrate 102, substantially eliminating charge carrier transport between the high work function layer 108 and the substrate 102. The substrate 102 has a second work function, which is smaller than the first work function of the high work function layer 108. In some embodiments, the substrate 102 is or comprises a semiconductor material, such as silicon or germanium, and has a second work function between 4.5 and 4.9 eV. The work function difference between the high work function layer 108 and the substrate 102 results in a depletion region (see 202 in Figures 2A and 2B) formed within the substrate 102. The depletion region (see 202 in Figures 2A and 2B) surrounds the outer surface of the DTI structure 104, passivating the damaged inner sidewalls 102d of the substrate 102. This passivation reduces the amount of noise in signals received from semiconductor devices that would otherwise be exposed to the damaged inner sidewalls 102d of the substrate 102. This passivation further reduces current leakage in the photodetector array surrounded by the DTI structure 104.

[0014] As shown in cross-sectional view 100b of FIG1B, in some embodiments, a third dielectric layer 114 comprising a material different from the second dielectric layer 112 extends between the high work function layer 108 and the insulating filler 110. As shown in cross-sectional view 100c of FIG1C, in some embodiments, a fourth dielectric layer 116 comprising a material different from the first dielectric layer 106 separates the first dielectric layer 106 from the high work function layer 108. In some embodiments, the third dielectric layer 114 and the fourth dielectric layer 116 provide additional insulation between the high work function layer 108 and the substrate 102 or the insulating filler 110.

[0015] Figures 2A and 2B illustrate the energy band diagram 200a and the corresponding cross-sectional view 200b of a DTI structure having a high work function layer separated from the substrate by a first dielectric layer in some embodiments. Figures 2A and 2B are described simultaneously.

[0016] The first Fermi level 204 of the high work function layer 108, and the second Fermi level 206, valence band 208, and conduction band 210 of the substrate 102 are shown. The first Fermi level 204, the second Fermi level 206, the valence band 208, and the conduction band 210 are positioned according to the energy levels of the bands (shown on the vertical axis) and the horizontal positions of the high work function layer 108, the first dielectric layer 106, and the substrate 102 shown in the cross-sectional view 200b (shown on the horizontal axis). When the system containing the high work function layer 108, the first dielectric layer 106, and the substrate 102 is in equilibrium, the first Fermi level 204 and the second Fermi level 206 have substantially the same energy level.

[0017] The first work function of the high work function layer 108 is the difference between the first Fermi level 204 and the vacuum level 212 of the high work function layer 108. Since the first work function is greater than the second work function, the vacuum level 212 of the substrate 102 is lower than the vacuum level 212 of the high work function layer 108. The vacuum level 212 is continuous throughout the band diagram 200a, therefore the vacuum level 212 rises in a portion of the region between the substrate 102 and the first dielectric layer 106 to reach the vacuum level 212 of the high work function layer 108. The energy difference between the vacuum level 212, the conduction band 210, and the valence band 208 of the substrate 102 remains substantially the same in the affected region, resulting in a corresponding energy rise in the conduction band 210 and the valence band 208 near the interface between the substrate 102 and the first dielectric layer 106. The valence band 208 near the interface is closer to the second Fermi level 206 than the valence band 208 located in the outer region 214 of the substrate 102, which is farther from the first dielectric layer 106. Furthermore, the conduction band 210 near the interface is farther from the second Fermi level 206 than the conduction band 210 located in the outer region 214 of the substrate 102, which is farther from the first dielectric layer 106.

[0018] The difference in proximity between the conductive band 210 and the second Fermi level 206 indicates that the electron concentration (not shown) in the depletion region 202 is lower than that in the outer region 214, resulting in a higher concentration of holes 216 remaining in the depletion region 202. The combination of the higher concentration of holes 216 and the lower electron probability in the depletion region 202 passivates the interface between the substrate 102 and the first dielectric layer 106, reducing the electronic interaction between the damaged inner sidewall 102d of the substrate and the devices in the outer region 214 of the substrate 102.

[0019] Figures 3A, 3B and 3C illustrate cross-sectional views 300a, 300b and 300c of an image sensor having a DTI structure including a high work function layer in some embodiments, wherein the DTI structure extends from a first surface of the substrate to a second surface.

[0020] As shown in the cross-sectional view 300a of FIG3A, in some embodiments, a plurality of photodetectors 302 are distributed in an array within a substrate 102. The plurality of photodetectors 302 are located within a photodetector region 301. The plurality of photodetectors include n-type doped regions (e.g., n-type dopants having a concentration greater than 10¹² atoms / cm³). The photodetectors in the plurality of photodetectors 302 are separated from each other by a DTI structure 104. In some embodiments, the DTI structure extends from a first surface 102a of the substrate 102 to a second surface 102b of the substrate 102 and physically / materially isolates portions of the substrate 102 containing the different photodetectors in the plurality of photodetectors 302.

[0021] A plurality of semiconductor devices 304 are located on a second surface 102b of substrate 102. In some embodiments, the plurality of semiconductor devices 304 are or include transistor devices (e.g., planar field-effect transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) devices, etc.). In some embodiments, the plurality of semiconductor devices 304 are or include transmission transistors for image sensor circuitry. In a further embodiment, the image sensor includes two bonding substrates, and the plurality of semiconductor devices 304 further include a reset transistor, a source follower transistor, a row select transistor, or similar elements. In other embodiments, the image sensor includes three bonding substrates, and the plurality of semiconductor devices 304 on substrate 102 do not include a reset transistor, a source follower transistor, or a row select transistor.

[0022] Interconnect structure 306 is located on the second surface 102b of substrate 102. Interconnect structure 306 is coupled to the plurality of semiconductor devices 304 and includes a plurality of wiring layers and via layers that couple the plurality of semiconductor devices 304 to other elements (not shown) of the image sensor, such as reset transistors, source follower transistors and row select transistors in an image sensor using three bonded substrates, or application-specific integrated circuits (ASICs) such as image processing circuitry in an image sensor using two bonded substrates.

[0023] A plurality of color filters 308 and microlenses 310 are located on a first surface 102a of a substrate 102. In some embodiments, the color filters 308 extend to cover two or more photodetectors and are separated from each other by insulating barriers 309 covering a metal mesh structure 315. The color filters 308 are centered on a segment of a DTI structure 104 extending between two or more photodetectors. The insulating barriers 309 include a plurality of segments that directly cover the segments of the DTI structure 104. In some embodiments, the microlenses 310 are centered on the DTI structure 104 extending between two or more photodetectors. In other embodiments, the microlenses 310 extend to cover the DTI structure 104 extending between two or more photodetectors, but are offset laterally from the DTI structure 104.

[0024] In some embodiments, the conductive channel 311 extends in the peripheral region 303 between the first surface 102a and the second surface 102b of the substrate. The conductive channel 311 includes a p-type doped channel 314 surrounded by an n-type doped well 312. The contacts of the interconnect structure 306 couple the conductive channel 311 to the interconnect structure on the second surface 102b, while the conductive plug 313 couples the conductive channel 311 to a high work function layer 108 of the DTI structure on the first surface 102a. During operation, the high work function layer 108 is biased to induce a higher concentration of holes in the depletion region (see 202 in FIG. 2A) (see 216 in FIG. 2A), further enhancing the passivation effect.

[0025] In some embodiments, a conductive pad structure 316 is formed in a substrate 102. The conductive pad structure 316 has exposed wires 318 accessible from a first surface 102a of the substrate 102. A plurality of insulating layers 320 isolate the exposed wires 318 from the substrate 102. In some embodiments, the conductive pad structure 316 is configured for testing an integrated device prior to implementation. In other embodiments, the conductive pad structure 316 is coupled to a conductive channel 311 via a first wiring 322 of an interconnection structure 306 and is configured to bias a high work function layer 108 when a voltage bias is applied to the exposed wires 318.

[0026] As shown in cross-sectional view 300b of FIG3B, in some embodiments, the conductive channel (see 311 in FIG3A) is omitted, and the high work function layer 108 is not biased during operation. As shown in cross-sectional view 300c of FIG3C, in some embodiments, the high work function layer 108 does not extend across the lowest surface 110a of the insulating filler 110. The lowest surface 110a is the surface of the insulating filler 110 that is closest to and faces the second surface 102b of the substrate 102. The high work function layer 108 has a lowest point between the first surface 102a and the lowest surface 110a and includes multiple regions physically / solidally isolated by the insulating filler 110. In a further embodiment, the depletion region 202 surrounds the first portion 104a of the DTI structure 104, but not the second portion 104b of the DTI structure 104. In other embodiments, a reduced depletion region (not shown) (e.g., a depletion region with a lower hole concentration than depletion region 202) surrounds a second portion 104b of the DTI structure 104.

[0027] Figures 4A, 4B, 4C, and 4D illustrate cross-sectional views 400a, 400b, 400c, and a top view 400d of an image sensor including a DTI structure 104. The DTI structure 104 has a first segment 402 extending from a first surface 102a of a substrate 102 to a second surface 102b, and a second segment 404 whose bottom surface is located between the first surface 102a and the second surface 102b of the substrate 102. Figures 4A and 4B are described simultaneously. The cross-sectional view of Figure 4A is taken along line A-A' of Figure 4D.

[0028] In some embodiments, the etch stop layer 406 extends below the first segment 402. In some embodiments, the floating diffusion region 408 forms a path for charge to enter the interconnect structure 306 from a plurality of photodetectors 302. The second segment 404 extends above the floating diffusion region 408. In some embodiments, the first segment 402 is laterally offset from the floating diffusion region 408 and laterally surrounds the photodetectors. In other embodiments, the first segment 402 is located at intersections of the DTI structure 104 adjacent to intersections directly covering the floating diffusion region 408, without surrounding the photodetectors 302 on the side opposite to the intersections covering the floating diffusion region 408. In some embodiments, the p-type doped region 410 within the substrate 102 extends to the second surface 102b of the substrate 102 and surrounds the outer sidewall of the DTI structure 104. During operation, the transmission transistors of multiple semiconductor devices 304 are biased to form a conductive channel between the photodetector and the floating diffusion region 408 through the p-type doped region 410. The p-type doped region 410 is also referred to as the positive doped region.

[0029] In some embodiments, as shown in the cross-sectional view 400c of FIG4C, the high work function layer 108 extends into the p-type doped region 410, but does not extend between the lowest surface 110a of the insulating filler 110 and the second surface 102b of the substrate 102. That is, the high work function layer 108 extends into the p-type doped region 410, and the insulating filler 110 extends further from the first surface 102a of the substrate 102 than the high work function layer 108. In other embodiments, the point of the high work function layer 108 furthest from the first surface 102a is spaced apart from the p-type doped region 410 in a direction perpendicular to the first surface 102a of the substrate 102.

[0030] As shown in the top view 400d of FIG4D, in some embodiments, the first segment 402 extends in a cross shape from a top view. In some embodiments, the second segment 404 (shown in dashed lines) extends over the common floating diffusion region 408 and over the intersection of the DTI structure 104 diagonally opposite to the intersection directly covering the floating diffusion region 408. In other embodiments, the first segment 402 extends over the intersection of the DTI structure 104 diagonally opposite to the intersection directly covering the floating diffusion region 408 and extends between intersections that do not directly cover the floating diffusion region 408. The transmission transistor of the semiconductor device 304 surrounds the floating diffusion region 408. In some embodiments, the photodetector 302 covers the transmission transistor and partially covers the p-type doped region 410.

[0031] Figures 5A, 5B, 5C, and 5D illustrate cross-sectional views 500a, 500b, 500c, and a top view 500d of some embodiments of an image sensor including a DTI structure 104 with an extension portion into the substrate 102. Figures 5A, 5B, 5C, and 5D are described simultaneously. The cross-sectional view of Figure 5A is taken along line A-A' of Figure 5D. In some embodiments, the DTI structure 104 consists of a second segment 404. In other words, the DTI structure 104 does not extend to the second surface 102b, and the depth 502 of the DTI structure 104 extending in the substrate 102 is substantially equal throughout the DTI structure 104 (e.g., within 5% of the average value).

[0032] FIG6 illustrates a cross-sectional view 600 of an image sensor having a DTI structure 104 comprising a second dielectric layer 112 lining the inner sidewall of a high work function layer 108. In some embodiments, the second dielectric layer 112, the high work function layer 108, and the first dielectric layer 106 have portions that directly cover a first surface 102a of a substrate 102, such that a first axis 602 extending in a first direction 604 perpendicular to the first surface 102a of the substrate 102 passes through portions of the high work function layer 108, the first dielectric layer 106, and the second dielectric layer 112. That is, the high work function layer 108 extends beyond the first surface 102a in the first direction 604 and extends across the first surface in a second direction 606 perpendicular to the first direction 604.

[0033] Figures 7A, 7B, 7C, and 7D illustrate cross-sectional views 700a, 700b, 700c, and 700d of an image sensor having a DTI structure 104 that includes a high work function layer that does not directly extend to cover the first surface 102a of the substrate. As shown in cross-sectional view 700a of Figure 7A, in some embodiments, the second dielectric layer 112, the high work function layer 108, and the first dielectric layer 106 do not directly cover portions of the first surface 102a of the substrate 102, and an additional insulating layer 702 extends to cover the first surface 102a of the substrate 102. That is, the high work function layer 108 is spaced apart from the first surface 102a of the substrate 102 by the first dielectric layer 106 in a second direction 606 parallel to the first surface 102a of the substrate 102. In a further embodiment, the high power function layer 108 does not extend beyond the lowest surface 110a of the insulating filler 110 in the first direction 604, causing the high power function layer 108 to become multiple electrical isolation rings surrounding the plurality of photodetectors 302.

[0034] As shown in the cross-sectional view 700b of FIG7B, in other embodiments, the first dielectric layer 106 includes a portion that directly covers the first surface 102a of the substrate 102, while the second dielectric layer 112 and the high work function layer 108 do not include portions that directly cover the first surface 102a of the substrate 102. An additional insulating layer 702 extends to cover the first surface 102a of the substrate 102. In some embodiments, the first dielectric layer 106 has a first outer surface 106s that faces the same direction (first direction 604) as the first surface 102a of the substrate 102, and the second dielectric layer 112 is spaced apart from the first surface 102a in a second direction 606 that is substantially parallel to the first surface 102a.

[0035] As shown in cross-sectional view 700c of FIG7C, in other embodiments, an additional insulating layer 702 and an additional dielectric layer 704 extend to cover a first surface 102a of substrate 102 and separate the color filter 308 from substrate 102. As shown in cross-sectional view 700d of FIG7D, in other embodiments, the additional insulating layer 702 and the additional dielectric layer 704 are spaced apart from substrate 102 by a first dielectric layer 106. In some embodiments, a high power function layer 108 covers the inner sidewalls of a first portion 106a of the first dielectric layer 106 but does not cover a second portion 106b of the first dielectric layer 106. In a further embodiment, since the high power function layer 108 does not contact other portions of the high power function layer 108 by extending to cover the first surface 102a of substrate 102 or extending between the lowest surface 110a and the second surface 102b of insulating filler 110, and the high power function layer 108 includes a plurality of electrically isolated rings surrounding a plurality of photodetectors 302.

[0036] Figures 8-16 illustrate a series of cross-sectional views 800-1600 of some embodiments of a method for forming an image sensor having a DTI structure including a high work function layer. Although Figures 6-14 are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions illustrated and / or described may be omitted in whole or in part.

[0037] As shown in the cross-sectional view 800 of FIG8, a plurality of photodetectors 302, a floating diffusion region 408, and a p-type doped region 410 are formed within the photodetector region 301 of the substrate 102. In some embodiments, the plurality of photodetectors 302 are or comprise an n-type region of the substrate formed using an implantation process. The floating diffusion region 408 is formed on the second surface 102b of the substrate 102. In some embodiments, the floating diffusion region 408 is or comprises an n-type region (e.g., a substrate region with n-type doping) formed using an implantation process. The p-type doped region 410 is or comprises a substrate region with p-type doping formed using an implantation process prior to the formation of the floating diffusion region 408. The p-type doped region 410 extends from the second surface 102b of the substrate 102 toward the first surface 102a of the substrate 102. In some embodiments, the p-type doped region 410 extends in a grid pattern corresponding to the grid pattern and position of the DTI structure (see 104 in FIG1A) to be formed thereafter. In some embodiments, the substrate 102 is or comprises a semiconductor material, such as silicon (Si), germanium (Ge), or the like. In some embodiments, the n-type dopant is or comprises one or more of phosphorus (P), arsenic (As), bismuth (Bi), lithium (Li), or the like. In some embodiments, the p-type dopant is or comprises one or more of boron (B), aluminum (Al), gallium (Ga), or the like.

[0038] In some embodiments, the conductive channel 311 is formed within the substrate 102. The conductive channel 311 forms an n-type doped well 312 by implanting an n-type dopant, and a p-type doped channel 314 is formed within the n-type doped well 312 by implanting a p-type dopant. During operation, the n-type doped well 312 reduces the number of photoelectrons attracted from the photodetector to the p-type doped channel 314. The conductive channel 311 is formed in the peripheral region 303 of the substrate 102.

[0039] As shown in the cross-sectional view 900 of FIG9, a plurality of semiconductor devices 304 are formed on the second surface of the substrate 102. In some embodiments, a patterned etching step is performed to remove a portion of the substrate 102, such that the resulting semiconductor devices 304 extend into the substrate 102. After the etching step, a plurality of deposition (e.g., physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD) or similar processes) and patterned etching (e.g., dry etching or similar processes) steps are performed to form a gate dielectric layer 902 and a gate electrode 904.

[0040] In some embodiments, the formation of the gate electrode 904 further includes forming a sacrificial gate layer, patterning the sacrificial gate layer and the gate dielectric layer 902, forming an interlayer dielectric surrounding the patterned sacrificial gate layer, and replacing the sacrificial gate layer with the gate electrode 904 by removing the sacrificial gate layer, forming a conformal conductive layer, and performing a planarization process (e.g., chemical mechanical planarization (CMP) process) to remove portions of the conformal conductive layer on the interlayer dielectric. In other embodiments, the semiconductor device 304 is formed by forming a conformal gate electrode layer on the conformal gate dielectric layer and patterning the conformal gate electrode layer and the conformal gate dielectric layer to form the gate dielectric layer 902 and the gate electrode 904. In some embodiments, an insulating spacer 906 is formed around the gate electrode 904 by forming a conformal insulating layer on the gate electrode 904 and then performing a self-aligned etching process (e.g., a non-patterned etching process), resulting in vertical portions of the conformal insulating layer remaining as the insulating spacer 906. In other embodiments, the semiconductor device 304 is formed using other processes, or different devices are formed using a variety of different processes.

[0041] As shown in the cross-sectional view 1000 of FIG10, an interconnect structure 306 is formed on the second surface 102b of the semiconductor device 304 and the substrate 102. The interconnect structure includes a contact 1002 extending from the semiconductor device 304 and the floating diffusion region 408 to the first wiring level 1004. In some embodiments, the contact 1002 also couples a conductive channel 311 to the first wiring 1006 of the first wiring level 1004. In some embodiments, the interconnect structure 306 is formed by depositing an interlayer dielectric 1008 and using one or more damascene processes, dual damascene processes, or similar processes. In some embodiments, multiple additional wiring levels (not shown) and via levels (not shown) are formed on the first wiring level by depositing additional interlayer dielectric layers and performing additional damascene processes, dual damascene processes, or similar processes. In some embodiments, the interconnect structure 306 is or contains a conductive material, such as gold (Au), copper (Cu), aluminum (Al), doped polycrystalline silicon, or other similar materials.

[0042] In some embodiments, prior to forming the interconnect structure 306, an etch stop layer (see Figure 4A 406) is formed on the second surface 102b of the substrate 102 using a deposition process and a subsequent patterning process (e.g., forming and patterning a mask layer, and then patterning an etch stop layer according to the mask layer (see Figure 4A 406)). In some embodiments, the etch stop layer (see Figure 4A 406) is or contains an insulating material, such as silicon nitride (Si₃N₄) or a similar material. In some embodiments, the interlayer dielectric is or contains an insulating material, such as silicon dioxide (SiO₂) or a similar material.

[0043] As shown in the cross-sectional view 1100 of FIG11, a first masking layer 1104 is formed on a first surface 102a of a substrate 102. In some embodiments, the first masking layer 1104 is formed using a deposition process, a spin coating process, an immersion process, or a similar process. The first masking layer 1104 is then patterned. In some embodiments, the first masking layer 1104 is a photoresist and is patterned using photolithography. The openings in the first masking layer 1104 correspond to the positions of the DTI structure to be formed later (see 104 in FIG1A and 5A).

[0044] After the first mask layer 1104 is patterned, a first etching process 1102 is performed. In some embodiments, the first etching process 1102 is an anisotropic dry etching process. The first etching process results in the formation of a plurality of first openings 1106 corresponding to the locations of the DTI structure (see 104 in FIG. 1A, 5A). The plurality of first openings 1106 extend into the p-type doped region 410. In some embodiments, the plurality of first openings 1106 extend to the second surface 102b of the substrate 102. In other embodiments, additional masking and etching processes are performed such that the openings corresponding to the first segment (see 402 in FIG. 4A) of the DTI structure (see 104 in FIG. 4A) extend to the second surface 102b of the substrate 102, while the second segment (see 404 in FIG. 4B) of the DTI structure (see 104 in FIG. 4A) is spaced apart from the second surface 102b by the substrate 102.

[0045] As shown in the cross-sectional view 1200 of FIG12, a first dielectric layer 106 is formed in a plurality of first openings 1106. In some embodiments, the first dielectric layer 106 is or comprises one or more of silicon dioxide (SiO₂), tantalum pentoxide (Ta₂O₅), titanium oxide (TiO₂), silicon nitride (Si₃N₄), or similar materials. In some embodiments, the first dielectric layer 106 is formed using one or more PVD, ALD, CVD, or similar methods.

[0046] As shown in the cross-sectional view 1300 of FIG13, a high work function layer 108 is formed in a plurality of first openings 1106 and is located above the first dielectric layer 106. The high work function layer 108 is separated from the substrate 102 by the first dielectric layer 106. In some embodiments, the high work function layer 108 covers the inner sidewall of a first portion of the first dielectric layer 106 (see 106a in FIG7D) but does not cover the second portion of the first dielectric layer (see 106b in FIG7D) (for example, the high work function layer partially covers the inner sidewall of the first dielectric layer 106, as shown in FIG3C, 4C, 5C and 7D).

[0047] In some embodiments, the high work function layer 108 is formed using one or more of PVD, ALD, CVD, or similar methods. In some embodiments, the high work function layer 108 is or comprises a metal oxide. In further embodiments, additional processing (e.g., annealing in an oxygen-rich environment, oxygen plasma surface treatment, etc.) is performed to increase the oxygen content and first work function of the metal oxide material to be equal to or greater than 5 eV. In other embodiments, the high work function layer 108 is or comprises a metal with a work function greater than 5 eV, such as gold (Au), platinum (Pt), or similar materials.

[0048] As shown in the cross-sectional view 1400 of FIG14, an insulating filler 110 is formed in a plurality of first openings 1106 (shown in dashed lines) above the first dielectric layer 106 and the high work function layer 108. The insulating filler 110 fills the plurality of first openings 1106 and extends beyond the first surface 102a of the substrate 102. In some embodiments, the insulating filler 110 is formed using one or more of PVD, ALD, CVD, or similar methods. In some embodiments, the insulating filler 110 is or contains an insulating material, such as silicon dioxide (SiO₂) or a similar material. In some embodiments, a second dielectric layer (see 112 in FIG1A, 6) is formed on the high work function layer 108 prior to the formation of the insulating filler 110.

[0049] In some embodiments, the high work function layer 108 is or comprises a metal or an opaque metal oxide, and a removal process is performed to remove a portion of the high work function layer 108 that directly covers the first surface 102a of the substrate 102. This removal process is or comprises an etching or planarization process. In a further embodiment, the first dielectric layer 106 is also removed from the first surface 102a of the substrate 102. In other embodiments, after the removal of the first dielectric layer 106, the first dielectric layer 106 remains on the first surface 102a of the substrate 102 (e.g., see Figures 7A, 7B). In embodiments where a portion of the high work function layer 108 is removed, an additional dielectric layer (see 704 in Figures 7C, 7D) and / or an additional insulating layer (see 702 in Figures 7C, 7D) is formed on the first surface 102a of the substrate 102. This method continues from embodiments where the high work function layer 108 is or comprises a transparent metal oxide and is not affected by the above-described removal process. In embodiments where the high work function layer 108 is affected by the removal process, the formation of the conductive plug (see 313 in Figures 3A, 15) and the formation of the conductive channel 311 are omitted.

[0050] As shown in the cross-sectional view 1500 of FIG15, a conductive plug 313 and a metal mesh structure 315 are formed on a first surface 102a of a substrate 102. In some embodiments, the conductive plug 313 and the metal mesh structure 315 are formed simultaneously by etching an opening through an insulating filler 110 to expose a conductive channel 311 (or an additional insulating layer (see 702 in FIG7A-7D)), forming a conformal metal layer, and patterning the conformal metal layer into the conductive plug 313 and the metal mesh structure 315. In other embodiments, the conductive plug 313 and the metal mesh structure 315 are formed using a damascene process within a sacrificial layer, and then the sacrificial layer is removed. In other embodiments, the conductive plug 313 and the metal mesh structure 315 are formed using a non-simultaneous process. In some embodiments, the insulating barrier 309 and the metal mesh structure 315 are patterned using the same patterning process. In some embodiments, the insulating cap 319 on the conductive plug 313 and the conductive plug 313 are patterned using the same patterning process. In a further embodiment, the insulating barrier 309 and the insulating cap 319 are patterned from the same insulating layer.

[0051] In some embodiments, the conductive pad structure (see 316 in FIG. 3A) is formed prior to the formation of the metal mesh structure 315 or the conductive plug 313. The conductive pad structure (see 316 in FIG. 3A) is formed using multiple etching and deposition processes, resulting in the conductive pad structure (see 316 in FIG. 3A) having exposed conductors (see 318 in FIG. 3A) coupled to the first wiring layer 1004. The exposed conductors (see 318 in FIG. 3A) are covered by sacrificial filler during the formation of the microlens (see 310 in FIG. 3A, 16). The exposed conductors (see 318 in FIG. 3A) are subsequently exposed by removing the sacrificial filler.

[0052] As shown in the cross-sectional view 1600 of FIG16, a plurality of color filters 308 and a plurality of microlenses 310 are formed in the photodetector region on the first surface 102a of the substrate 102. In some embodiments, the plurality of color filters 308 are formed such that the filters independently cover two different photodetectors (e.g., filter 1601 extends directly to cover the first photodetector 1602 and the second photodetector (not shown), but does not cover the third photodetector 1604 and the fourth photodetector (not shown)). In other embodiments, the plurality of color filters 308 are formed such that the filters independently cover four different photodetectors. The plurality of color filters 308 are separated by a metal mesh structure 315 and an insulating barrier 309. In some embodiments, an insulating conformal layer 1606 is formed prior to the formation of the plurality of color filters 308, and the plurality of color filters 308 are spaced apart from the metal mesh structure 315 and the insulating barrier 309.

[0053] In some embodiments, the microlenses 310 are positioned such that each microlens is individually located at the center of the plurality of color filters 308. In other embodiments, the plurality of microlenses 310 are offset from the center of the color filters according to their position on the photodetector array. That is, a microlens 310 located near the central portion of the photodetector array may be located at the center of the color filter 308 directly below it, while a microlens 310 located near the edge of the photodetector array may be offset from the center of the color filter 308 to more effectively capture light incident at an angle.

[0054] Figure 17 illustrates a flowchart 1700 of some embodiments, which is a method for forming an image sensor having a DTI structure including a high work function layer. Although this method and other methods illustrated and / or described herein are illustrated as a series of actions or events, it will be understood that this disclosure is not limited to the illustrated order or actions. Therefore, in some embodiments, these actions may be performed in a different order than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

[0055] In box 1702, multiple photodetectors are formed within the substrate. An example illustrating this step can be found in Figure 8.

[0056] In box 1704, a plurality of transmission transistors are formed on the substrate. An example illustrating this step can be found in Figure 9.

[0057] In block 1706, an interconnect structure is formed on the transmission transistor, the interconnect structure including contacts extending to the transmission transistor. An example illustrating this step can be found in Figure 10.

[0058] In box 1708, multiple trenches are etched into the first surface of the substrate, the first surface of the substrate facing away from the interconnect structure. An example illustrating this step can be found in Figure 11.

[0059] In box 1710, a first dielectric layer is formed on a first surface of the substrate and the first dielectric layer lining the inner sidewalls of the plurality of trenches. An example illustrating this step can be found in Figure 12.

[0060] In box 1712, a high work function (WF) layer comprising a metal or metal oxide is formed on the first surface of the substrate, and the high work function layer covers a first portion of the inner sidewall of the first dielectric layer. An example illustrating this step can be found in Figure 13.

[0061] In box 1714, insulating filler is deposited into the multiple trenches to fill them. An illustrated example of this step can be found in Figure 14.

[0062] In box 1716, a color filter array and a plurality of microlenses are formed on the first surface of the substrate. An example illustrating this step can be found in Figure 16.

[0063] Some embodiments relate to an integrated device including: a substrate having a first surface and a second surface opposite to the first surface; a plurality of photodetectors located on the substrate and arranged in a grid pattern; and a deep trench isolation (DTI) structure extending between the plurality of photodetectors, the DTI structure including: a first dielectric layer located on the first surface and extending to the second surface; a high work function (WF) layer comprising a metal or metal oxide and spaced from the substrate by the first dielectric layer; a second dielectric layer, wherein a first portion of the second dielectric layer is spaced from the first dielectric layer by the high work function layer; and an insulating filler extending between the inner sidewalls of the second dielectric layer; wherein the high work function layer has a WF greater than 5 electron volts.

[0064] Other embodiments relate to an integrated device, including: a substrate having a first surface and a second surface; a first dielectric layer extending into the substrate from the first surface to the second surface and having an inner sidewall; a high work function (WF) layer lining the inner sidewall of the first dielectric layer and having an inner sidewall; a second dielectric layer lining the inner sidewall of the high work function layer; and an insulating filler extending between the inner sidewalls of the second dielectric layer; wherein the high work function layer has a work function greater than 5 electron volts.

[0065] Other embodiments relate to a method of forming an integrated device, comprising: forming a plurality of photodetectors in a substrate; forming a plurality of transmission transistors on the substrate; forming an interconnect structure on the transmission transistors, the interconnect structure including contacts extending to the transmission transistors; etching a plurality of trenches into the substrate on a first surface of the substrate, the first surface of the substrate facing away from the interconnect structure; depositing a first dielectric layer on the first surface of the substrate and lining the inner sidewalls of the plurality of trenches; forming a high work function (WF) layer comprising a metal or metal oxide on the first surface of the substrate and covering a first portion of the inner sidewalls of the first dielectric layer; and depositing an insulating filler into the plurality of trenches to fill the plurality of trenches.

[0066] It should be understood that in this written description, and in the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of explanation to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0067] The foregoing has summarized the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0068] The aspects of this disclosure are most readily understood when reading the accompanying drawings. These drawings are drawn to clearly illustrate relevant aspects of the embodiments. These drawings may illustrate the relationships between various structures and / or elements in the embodiments. It should be noted that these drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A, 1B, and 1C illustrate cross-sectional views of some deep trench isolation (DTI) structure embodiments including high work function (WF) layers. Figures 2A and 2B illustrate energy band diagrams and corresponding cross-sectional views of some DTI structure embodiments having high work function layers separated from the substrate by a first dielectric layer. Figures 3A, 3B, and 3C illustrate cross-sectional views of some image sensor embodiments, wherein the image sensor has a DTI structure including a high work function layer, the DTI structure extending from a first surface of the substrate to a second surface. Figures 4A, 4B, 4C, and 4D illustrate cross-sectional and top views of an image sensor including a DTI structure having a first segment extending from the first surface of the substrate to the second surface and a second segment partially extending into the substrate. Figures 5A, 5B, 5C, and 5D illustrate cross-sectional and top views of an image sensor, which includes a DTI structure partially extending into the substrate. Figure 6 illustrates a cross-sectional view of an image sensor whose DTI structure includes a second dielectric layer that lining the inner sidewalls of a high work function layer. Figures 7A, 7B, 7C, and 7D illustrate cross-sectional views of an image sensor whose DTI structure includes a high work function layer that does not directly extend above the first surface of the substrate. Figures 8-16 illustrate a series of cross-sectional views illustrating some embodiments of methods for forming an image sensor containing a DTI structure with a high work function layer. Figure 17 illustrates a flowchart of some embodiments of methods for forming an image sensor containing a DTI structure with a high work function layer.

Claims

1. An integrated device, comprising: The substrate includes a first surface and a second surface opposite to the first surface; Multiple photodetectors are located within the substrate and arranged in a grid pattern; The deep trench isolation structure extends between the plurality of photodetectors, the deep trench isolation structure comprising: a first dielectric layer located on the first surface and extending toward the second surface; a high work function layer comprising a metal or metal oxide and spaced apart from the substrate by the first dielectric layer; a second dielectric layer, wherein a first portion of the second dielectric layer is spaced apart from the first dielectric layer by the high work function layer; and an insulating filler extending between the inner sidewalls of the second dielectric layer; wherein the high work function layer has a work function greater than 5 electron volts.

2. The integrated device as claimed in claim 1, wherein the high work function layer comprises a transparent metal oxide, and wherein a first axis extending perpendicular to the first surface of the substrate passes through a portion of the high work function layer, wherein the transparent metal oxide of the high work function layer extends from a first side of the high work function layer contacting the first dielectric layer to a second side of the high work function layer contacting the second dielectric layer.

3. The integrated device of claim 1, wherein the high power function layer comprises a metal and is spaced apart from the first surface of the substrate by a first dielectric layer in a direction parallel to the first surface of the substrate, wherein the metal of the high power function layer extends from a first side of the high power function layer contacting the first dielectric layer to a second side of the high power function layer contacting the second dielectric layer.

4. The integrated device as claimed in claim 1, wherein a second portion of the second dielectric layer contacts the first dielectric layer.

5. The integrated device as claimed in claim 1, wherein the first portion of the second dielectric layer extends beneath the insulating filler.

6. An integrated device, comprising: A substrate includes a first surface and a second surface; a first dielectric layer extends from the first surface to the second surface and includes internal sidewalls; A high work function layer, lining and including the inner sidewalls of the first dielectric layer; a second dielectric layer, lining the inner sidewalls of the high work function layer; and an insulating filler extending between the inner sidewalls of the second dielectric layer; wherein the high work function layer has a work function greater than 5 electron volts.

7. The integrated device of claim 6, wherein the first dielectric layer further comprises a first portion located between the first surface and the second surface of the substrate, and a second portion spaced apart from the second surface by the first surface of the substrate, wherein the first dielectric layer has a first outer surface facing in the same direction as the first surface of the substrate, and wherein the second dielectric layer is spaced apart from the first outer surface in a direction substantially parallel to the first outer surface.

8. The integrated device as claimed in claim 6, further comprising a doped region of the substrate containing a p-type dopant, wherein a first portion of the first dielectric layer extends between the first surface and the doped region, wherein a second portion of the first dielectric layer extends into the doped region.

9. A method of forming an integrated device, comprising: Multiple photodetectors are formed within the substrate; Multiple transmission transistors are formed on the substrate; An interconnect structure is formed on the transmission transistor, the interconnect structure including a contact extending to the transmission transistor; a plurality of trenches are etched into the substrate on a first surface of the substrate, the first surface of the substrate facing away from the interconnect structure; a first dielectric layer is deposited on the first surface of the substrate and lining the inner sidewalls of the plurality of trenches. A high work function layer comprising a metal or metal oxide is formed on the first surface of the substrate and covers a first portion of the inner sidewall of the first dielectric layer; and an insulating filler is deposited into the plurality of trenches to fill the plurality of trenches.

10. The method as described in claim 9, further comprising: After depositing the insulating filler, a portion of the high power function layer extending beyond the first surface of the substrate is removed, wherein a second portion of the inner sidewall of the first dielectric layer is exposed after the high power function layer is formed and before the insulating filler is deposited into the plurality of trenches; and wherein removing the portion of the high power function layer extending beyond the first surface of the substrate after depositing the insulating filler results in the high power function layer comprising a plurality of electrical isolation rings surrounding the plurality of photodetectors.

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