Integrated chip and method of manufacturing the same

Abstract

An integrated chip includes a first transistor along a frontside of a first semiconductor substrate. A first conductive interconnect is on the frontside of the first semiconductor substrate and coupled to a source / drain of the first transistor. A backside through-substrate via (BTSV) extends through the first semiconductor substrate from a backside of the first semiconductor substrate through the frontside of the first semiconductor substrate to the first conductive interconnect. A capacitor is along the backside of the first semiconductor substrate and extends into the first semiconductor substrate from the backside of the first semiconductor substrate. The capacitor includes a first electrode layer, a second electrode layer, and an insulator layer between the first electrode layer and the second electrode layer. The first electrode layer is coupled to the source / drain of the first transistor by the BTSV and the first conductive interconnect.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated wafer and a method for manufacturing the same. Prior Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors are widely used in various modern electronic devices, such as cameras, tablets, and smartphones. CMOS image sensors can be front-side illuminated (FSI) or back-side illuminated (BSI). Compared to FSI image sensors, BSI image sensors offer better sensitivity, superior angular response, and greater flexibility in metal wiring.

[0003] Many modern integrated circuits (ICs) include transistors and passive components. Examples of passive components include capacitors, resistors, inductors, and variable capacitors. Passive components are widely used to control IC characteristics such as gain and time constant. Some passive components include integrated passive devices (IPDs). An IPD is a collection of one or more passive components embedded in a single monolithic device and packaged as an integrated circuit (IC). Summary of the Invention

[0004] In some embodiments, this disclosure relates to an integrated wafer including a first transistor along the front side of a first semiconductor substrate. The first transistor includes a first source / drain, a second source / drain, and a gate. A first conductive interconnect is located on the front side of the first semiconductor substrate and coupled to the second source / drain of the first transistor. A back-side substrate via (BTSV) extends from the back side of the first semiconductor substrate through the front side of the first semiconductor substrate to the first conductive interconnect. A capacitor extends along and into the first semiconductor substrate from the back side of the first semiconductor substrate. The capacitor includes a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. The first electrode layer is coupled to the second source / drain of the first transistor through the BTSV and the first conductive interconnect.

[0005] In other embodiments, this disclosure relates to an integrated wafer of a photosensor included in a first semiconductor substrate of a first semiconductor wafer. A transfer transistor runs along the first semiconductor substrate. The transfer transistor includes a first source / drain coupled to the photosensor. A first pixel transistor runs along the front side of a second semiconductor substrate bonded to a second semiconductor wafer of the first semiconductor wafer. The first pixel transistor includes a first source / drain coupled to a second source / drain of the transfer transistor via a first conductive bonding pad and a second conductive bonding pad bonded together at an interface between the first and second semiconductor wafers. A back-side substrate via (BTSV) extends from the back side of the second semiconductor substrate through the front side of the second semiconductor substrate. The BTSV is coupled to the second source / drain of the first pixel transistor via a first conductive interconnect on the second semiconductor wafer. A lateral overflow integrating capacitor (LOFIC) runs along the back side of the second semiconductor substrate. The LOFIC includes a first electrode layer coupled to the BTSV and extending along the back side of the second semiconductor substrate and between the sidewalls of the second semiconductor substrate. The LOFIC includes a second electrode layer extending along the back side of the second semiconductor substrate, between the sidewalls of the second semiconductor substrate, and between the sidewalls of the first electrode layer. The LOFIC includes an insulating layer between the first electrode layer and the second electrode layer.

[0006] In other embodiments, this disclosure relates to a method of forming an integrated wafer. The method includes forming a first transistor along the front side of a first semiconductor substrate of a first semiconductor wafer. The first transistor includes a first source / drain, a second source / drain, and a gate. The method includes forming a first conductive interconnect coupled to a second source / drain of the first transistor on the front side of the first semiconductor substrate. The method includes etching the first semiconductor substrate from a back side to a front side to form a through-substrate via extending from the back side through the front side of the first semiconductor substrate and exposing a portion of the first conductive interconnect. The method includes depositing a conductive layer from the back side of the first semiconductor substrate in the through-substrate via and on a portion of the first conductive interconnect to form a back-side substrate via (BTSV). The method includes etching the first semiconductor substrate from a back side to a front side to form a capacitor trench in the first semiconductor substrate. The method includes depositing a first electrode layer, an insulating layer, and a second electrode layer in the capacitor trench and along the back side of the first semiconductor substrate to form a capacitor in the capacitor trench and along the back side of the first semiconductor substrate. The first electrode layer is coupled to the second source / drain of the first transistor through BTSV and the first conductive interconnect. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure are best understood by reading the following detailed description of the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 illustrates a cross-sectional view of some embodiments of an image sensor integrated chip, including a light sensor in a first semiconductor substrate, a pixel transistor coupled to the light sensor along the front side of a second semiconductor substrate, and a lateral overflow integration capacitor (LOFIC) coupled to the pixel transistor along the back side of the second semiconductor substrate and through a backside through-substrate via (BTSV). Figure 2 illustrates a circuit diagram of some embodiments of the integrated wafer in Figure 1. Figure 3 illustrates a cross-sectional view of some embodiments of the LOFIC 170 in Figure 1. Figure 4 illustrates a cross-sectional view of some embodiments of the integrated wafer in Figure 1, wherein the BTSV is coupled to the LOFIC through a conductive bonding contact window on the back side of the second semiconductor substrate. Figure 5 illustrates a top view of some embodiments of the integrated wafer in Figure 4. Figures 6 and 7 illustrate cross-sectional views of some embodiments of the integrated wafer in Figure 1, wherein the BTSV is coupled to the LOFIC through a back-side conductive via. Figure 8 illustrates a cross-sectional view of some embodiments of the integrated wafer in Figure 1, wherein the BTSV is directly coupled to the LOFIC. Figures 9 to 31 are cross-sectional views illustrating methods for forming an image sensor integrated wafer containing a LOFIC formed along the back side of a semiconductor substrate and coupled to a pixel transistor along the front side of the semiconductor substrate via BTSV. Figure 32 illustrates a flowchart of a method for forming an image sensor integrated wafer containing a LOFIC formed along the back side of a semiconductor substrate and coupled to a pixel transistor along the front side of the semiconductor substrate via BTSV. Implementation

[0008] The following disclosure provides numerous different embodiments or examples to achieve different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, to facilitate the description of the relationship between one element or feature and another shown in the figures, this document may use spatial relative terms such as "below," "lower," "lower," "above," and "higher." These spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0010] The image sensor integrated chip includes a photodetector and a transfer transistor located on a first semiconductor wafer. The image sensor also includes a pixel transistor and a lateral overflow integration capacitor (LOFIC) located on a second wafer bonded to the first semiconductor wafer. The pixel transistors are arranged along the front side of the semiconductor substrate of the second semiconductor wafer. A first source / drain of the pixel transistor is selectively coupled to the photodetector via the transfer transistor. A second source / drain of the pixel transistor is coupled to the LOFIC.

[0011] In some integrated circuits, the LOFIC is located on the front side of the semiconductor substrate. However, the space on the front side of the semiconductor substrate may be limited. For example, conductive interconnects on a second semiconductor wafer occupy most of the space on the front side of the semiconductor substrate. Furthermore, as the pixel pitch decreases, the space on the front side of the semiconductor substrate further decreases. Therefore, the size of the LOFIC may be limited, and consequently, the capacitance of the LOFIC may also be limited. As a result, the performance of the image sensor may be limited.

[0012] In the various embodiments disclosed herein, the LOFICs are arranged on the back side of the semiconductor substrate, where there is more available space, thus making it easier to increase the size of the LOFICs (and thus increase the capacitance). As a result, the performance of the image sensor may be improved. In various embodiments, the LOFICs are coupled to a second source / drain of the pixel transistor through a backside through-substrate via (BTSV), which extends from the back side of the semiconductor substrate through the semiconductor substrate to the front side of the semiconductor substrate.

[0013] Figure 1 illustrates a cross-sectional view 100 of some embodiments of an image sensor integrated chip including a LOFIC, including a light sensor 110 in a first semiconductor substrate 104, a pixel transistor 136 coupled to the light sensor 110 along the front side 134a of a second semiconductor substrate 134, and a lateral overflow integral capacitor (LOFIC) 170 coupled to the pixel transistor 136 along the back side 134b of the second semiconductor substrate 134 through a back substrate via (BTSV) 168.

[0014] The integrated wafer includes a first semiconductor wafer 102. The first semiconductor wafer 102 includes a first semiconductor substrate 104. A first pixel 106 and a second pixel 108 are arranged along the first semiconductor substrate 104. The first pixel 106 includes a first photosensor 110 in the first semiconductor substrate 104 and a first transfer transistor 114 along the first semiconductor substrate 104. The second pixel 108 includes a second photosensor 112 in the first semiconductor substrate 104 and a second transfer transistor 116 along the first semiconductor substrate 104. The first transfer transistor 114 includes a first source / drain 118, a second source / drain 120, and a gate 122. In some embodiments, the first photosensor 110 is a photodiode formed by the first source / drain 118 and the first semiconductor substrate 104.

[0015] A first dielectric structure 124 comprising multiple dielectric layers is located on a first semiconductor wafer 102. Conductive interconnects 126 (e.g., conductive contact windows, conductive vias, conductive interconnects, etc.) are located on the first semiconductor wafer 102 and within the first dielectric structure 124. A first conductive bonding contact window 128 and a first conductive bonding pad 130 are located on the first semiconductor wafer 102 and within the first dielectric structure 124.

[0016] The integrated wafer includes a second semiconductor wafer 132 bonded to a first semiconductor wafer 102. The second semiconductor wafer 132 includes a second semiconductor substrate 134. A first pixel transistor 136, a second pixel transistor 138, a third pixel transistor 140, and a fourth pixel transistor (e.g., 230 in FIG. 2) are arranged along the front side 134a of the second semiconductor substrate 134. The first pixel transistor 136 includes a first source / drain 142, a second source / drain 144, and a gate 146. The second pixel transistor 138 includes a first source / drain 148, a second source / drain 150, and a gate 152. The third pixel transistor 140 includes a first source / drain 154, a second source / drain 156, and a gate 158. In some embodiments, source / drain 154 and source / drain 150 are the same. A source / drain may refer to either a source or a drain, and may be referred to individually or collectively depending on the context.

[0017] A second dielectric structure 160, comprising multiple dielectric layers, is located on a second semiconductor wafer 132. Conductive interconnects 162 and 163 (e.g., conductive contact windows, conductive vias, conductive interconnects, etc.) are located on the second semiconductor wafer 132 and within the second dielectric structure 160. A second conductive bonding contact window 164 and a second conductive bonding pad 166 are located on the second semiconductor wafer 132 and within the second dielectric structure 160. The second conductive bonding pad 166 is bonded and coupled to the first conductive bonding pad 130 at the interface where the second semiconductor wafer 132 and the first semiconductor wafer 102 are joined. Furthermore, the second dielectric structure 160 is bonded to the first dielectric structure 124 at this interface. The source / drain 142 of transistor 136 and the gate 152 of transistor 138 are coupled to the source / drain 120 of transistors 114 and 116 through conductive interconnect 162, second conductive bonding contact window 164, second conductive bonding pad 166, first conductive bonding pad 130, first conductive bonding contact window 128 and conductive interconnect 126.

[0018] A backside through-substrate via (BTSV) 168 is located on the second semiconductor wafer 132. BTSV 168 extends from the back side 134b of the second semiconductor substrate 134 through the front side 134a of the second semiconductor substrate 134. BTSV 168 extends into the second dielectric structure 160 to the conductive interconnects on the second semiconductor wafer 132. BTSV 168 is coupled to the second source / drain 144 of the first pixel transistor 136 through conductive interconnects 163 (e.g., contact windows and conductive interconnects).

[0019] A back-side dielectric structure 182 and a lateral overflow integration capacitor (LOFIC) 170 are located on a second semiconductor wafer 132. The back-side dielectric structure 182 and LOFIC 170 are arranged along the back side 134b of the second semiconductor substrate 134. LOFIC 170 extends from the back side 134b of the second semiconductor substrate 134 into the second semiconductor substrate 134. LOFIC includes a first electrode layer 172, a second electrode layer 176, and an insulating layer 174 located between the first electrode layer 172 and the second electrode layer 176. A dielectric layer 178 is located (e.g., separating) the first electrode layer 172 and the second semiconductor substrate 134. As shown by line 180, the first electrode layer 172 is coupled to a BTSV 168 on the back side 134b of the second semiconductor substrate 134, and line 180 symbolizes the electrical connection between the first electrode layer 172 and the BTSV 168. Therefore, the first electrode layer 172 of the LOFIC 170 is coupled to the second source / drain 144 of the first pixel transistor 136 via BTSV 168 and conductive interconnect 163. Furthermore, the first pixel transistor 136 and the first transfer transistor 114 selectively couple the first electrode layer 172 of the LOFIC 170 to the first photosensor 110. The second electrode layer 176 is coupled to a reference voltage terminal (e.g., 242 in FIG. 2).

[0020] By arranging the LAFIC 170 along the back side 134b of the second semiconductor substrate 134, the capacitance of the LAFIC 170 can be increased, thereby improving the performance of the image sensor. For example, the back side 134b may have more available space than the front side 134a. Therefore, when the LAFIC 170 is configured along the back side 134b, the size of the LAFIC 170 (and therefore the capacitance of the LAFIC 170) can be increased more easily.

[0021] Figure 2 illustrates a circuit diagram 200 of some embodiments of the integrated chip in Figure 1.

[0022] In some embodiments, the photosensor 110 is a photodiode having a first terminal 202 (e.g., corresponding to a first semiconductor substrate 104) and a second terminal 204 (e.g., corresponding to a source / drain 118).

[0023] The first transfer transistor 114 has a first terminal 206 (e.g., corresponding to source / drain 118), a second terminal 208 (e.g., corresponding to source / drain 120), and a control terminal 210 (e.g., corresponding to gate 122). Terminal 206 is coupled to terminal 204.

[0024] The first pixel transistor 136 has a first terminal 212 (e.g., corresponding to source / drain 142), a second terminal 214 (e.g., corresponding to source / drain 144), and a control terminal 216 (e.g., corresponding to gate 146). Terminal 212 is coupled to terminal 208.

[0025] The second pixel transistor 138 (e.g., a source follower transistor) has a first terminal 218 (e.g., corresponding to source / drain 148), a second terminal 220 (e.g., corresponding to source / drain 150), and a control terminal 222 (e.g., corresponding to gate 152). The control terminal 222 is coupled to terminals 208 and 212. Terminal 218 is coupled to a supply voltage terminal 250 (e.g., VDD terminal).

[0026] The third pixel transistor 140 (e.g., a column select transistor) has a first terminal 224 (e.g., corresponding to source / drain 154), a second terminal 226 (e.g., corresponding to source / drain 156), and a control terminal 228 (e.g., corresponding to gate 158). Terminal 224 is coupled to terminal 220. Terminal 226 is coupled to output terminal 252.

[0027] The fourth pixel transistor 230 (e.g., a reset transistor) has a first terminal 232 (e.g., corresponding to a first source / drain), a second terminal 234 (e.g., corresponding to a second source / drain), and a control terminal 236 (e.g., corresponding to a gate). Terminal 232 is coupled to terminal 214. Terminal 234 is coupled to supply voltage terminal 250.

[0028] LOFIC 170 has a first terminal 238 (e.g., corresponding to the first electrode layer 172) and a second terminal 240 (e.g., corresponding to the second electrode layer 176). Terminal 238 is coupled to terminals 214 and 232. Terminal 240 is coupled to a reference voltage terminal 242 (e.g., ground).

[0029] Figure 3 illustrates a cross-sectional view 300 of some embodiments of the LOFIC 170 in Figure 1.

[0030] The first electrode layer 172 has a lateral portion located at a gap below the back side 134b of the semiconductor substrate 134, and a vertical portion extending from below the back side 134b to between the first sidewall 134c and the second sidewall 134d of the semiconductor substrate 134. A dielectric layer 178 separates the outer sidewalls 172a and 172b of the first electrode layer 172 from the sidewalls 134c and 134d of the semiconductor substrate 134. Furthermore, a dielectric layer 178 separates the upper surface 172c of the first electrode layer 172 from the lower surface 134e of the semiconductor substrate 134. The dielectric layer 178 extends below the back side 134b of the semiconductor substrate 134.

[0031] The second electrode layer 176 has a lateral portion located below the lateral portion of the first electrode layer 172 at a gap, and a vertical portion extending from below the back side 134b to between the sidewalls 134c and 134d of the semiconductor substrate 134. An insulating layer 174 separates the sidewalls 176a and 176b of the second electrode layer 176 from the inner sidewalls 172d and 172e of the first electrode layer 172. Furthermore, an insulating layer 174 separates the upper surface 176c of the second electrode layer 176 from the lower surface 172f of the first electrode layer 172.

[0032] In some embodiments, the LOFIC 170 may have additional electrode layers and additional insulating layers. For example, in some embodiments, the LOFIC 170 has a third electrode layer (not shown) located between the first electrode layer 172 and the insulating layer 174, and a second insulating layer (not shown) located between the third electrode layer and the first electrode layer 172. In these embodiments, the first electrode layer and the second electrode layer 176 are coupled together to form a first electrode, while the third electrode layer forms a second electrode separate from the first electrode.

[0033] Figure 4 illustrates a cross-sectional view 400 of some embodiments of the integrated wafer in Figure 1, wherein the BTSV 168 is coupled to the first electrode layer 172 of the LOFIC 170 through a back-side conductive bonding contact window 402 on the back side 134b of the second semiconductor substrate 134. Figure 5 illustrates a top view 500 of some embodiments of the integrated wafer in Figure 4. In some embodiments, the top view 500 of Figure 5 may be obtained, for example, along line A-A' of Figure 4.

[0034] Referring to Figures 4 and 5, the first electrode layer 172 extends directly beneath the BTSV 168, and the back-side conductive bonding contact window 402 extends from the back-side conductive bonding pad 404 through the first electrode layer 172 to the BTSV 168. The back-side conductive bonding contact window 402 directly contacts the sidewall 172g of the first electrode layer 172 and the lower surface of the BTSV 168, thereby coupling the BTSV 168 to the first electrode layer 172. The first electrode layer 172 laterally surrounds the back-side conductive bonding contact window 402. In some embodiments, the upper surface of the back-side conductive bonding contact window 402 is located on the lower surface of the BTSV 168. In other embodiments, the back-side conductive bonding contact window 402 extends slightly into the BTSV 168 (e.g., as shown by dashed line 438).

[0035] A back-side conductive bonding contact window 424 extends from the back-side conductive bonding pad 426 to the second electrode layer 176 and directly contacts the second electrode layer 176. In some embodiments, the upper surface of the back-side conductive bonding contact window 424 is located on the lower surface of the second electrode layer 176. In other embodiments, the back-side conductive bonding contact window 424 extends slightly into the second electrode layer 176 (e.g., as shown by dashed line 439).

[0036] In some cases, the cost and / or process time of the integrated wafer can be reduced by coupling the first electrode layer 172 to the BTSV 168 using the back-side conductive bonding contact window 402 and by directly coupling the back-side conductive bonding contact window 424 to the second electrode layer 176.

[0037] BTSV 168 has a lower surface below the back side 134b of semiconductor substrate 134 and an upper surface above the front side 134a of semiconductor substrate 134. Dielectric layer 434 is located between BTSV 168 and semiconductor substrate 134. Dielectric layer 434 extends along the sidewall of BTSV 168 from the lower surface to the upper surface. In some embodiments, the width of BTSV gradually decreases from the lower surface to the upper surface. In some embodiments, the upper surface of BTSV 168 is located on the bottom surface of the upper conductive interconnect 163. In other embodiments, BTSV 168 extends slightly into the upper conductive interconnect 163 (e.g., as shown by dashed line 436).

[0038] Figures 6 and 7 illustrate cross-sectional views 600 to 700 of some embodiments of the integrated wafer in Figure 1, wherein BTSV 168 is coupled to the first electrode layer 172 of LOFIC 170 through a back-side conductive via 602.

[0039] In some embodiments (e.g., as shown in FIG6), a back-side conductive via 602 extends from a back-side conductive interconnect 604 to a BTSV 168, and a back-side conductive via 606 extends from a back-side conductive interconnect 604 to a first electrode layer 172, thereby coupling the BTSV 168 to the first electrode layer 172.

[0040] In some embodiments (e.g., as shown in FIG7), a back-side conductive via 602 extends from a back-side conductive interconnect 604 through the first electrode layer 172 to the BTSV 168 and directly contacts the first electrode layer 172 and the BTSV 168, thereby coupling the BTSV 168 to the first electrode layer 172.

[0041] In some cases, the design flexibility of the integrated wafer can be improved by coupling the first electrode layer 172 to the BTSV 168 using back-side conductive interconnects 602, 604, and 606, and coupling the second electrode layer 176 to the back-side conductive bonding contact window 424 using back-side conductive interconnects 608 and 610.

[0042] Referring to Figures 6 and 7, the back-side conductive via 608 extends from the back-side conductive interconnect 610 to the second electrode layer 176, and the back-side conductive bonding contact window 424 extends from the back-side conductive bonding pad 426 to the back-side conductive interconnect 610.

[0043] Figure 8 illustrates a cross-sectional view 800 of some embodiments of the integrated wafer in Figure 1, wherein BTSV 168 is directly coupled to the first electrode layer 172 of LOFIC 170.

[0044] The first electrode layer 172 extends directly beneath the BTSV 168 and directly contacts the lower surface of the BTSV 168. In some embodiments, the first electrode layer covers the lower surface of the BTSV 168. In some cases, by directly coupling the first electrode layer 172 to the BTSV 168, the cost and / or process time of the integrated wafer can be reduced.

[0045] Referring to Figures 4 through 8, in some embodiments, reference transistor 410 selectively couples the second electrode layer 176 to a reference voltage terminal (e.g., 242 in Figure 2). In some embodiments, reference transistor 410 is located on a third semiconductor wafer 406 bonded to a second semiconductor wafer 132. The third semiconductor wafer 406 includes a third semiconductor substrate 408. Transistors 410 and 412 are arranged along the third semiconductor substrate 408. A third dielectric structure 414, conductive interconnects 416, conductive bonding contact windows 418, and conductive bonding pads 420 and 422 are located on the third semiconductor wafer 406. Conductive bonding pad 420 is bonded and coupled to a back-side conductive bonding pad 426 at the interface where the second semiconductor wafer 132 and the third semiconductor wafer 406 are bonded. Conductive bonding pad 422 is bonded and coupled to a back-side conductive bonding pad 404 at the same interface. The first source / drain 428 of the reference transistor 410 is coupled to the second electrode layer 176 through conductive bonding contact windows 424, 418, conductive bonding pads 426, 420 and conductive interconnect 416. The second source / drain 430 of the reference transistor 410 is coupled to a reference voltage terminal (e.g., 242 in FIG. 2).

[0046] In some embodiments, the back-side dielectric structure 182 includes a plurality of dielectric layers 440, 442, 444, and 446. In some embodiments, a shallow trench isolation (STI) structure 448 is located between pixel transistors on the second semiconductor wafer 132. In some embodiments, a deep trench isolation (DTI) structure 450 is located between pixels on the first semiconductor wafer 102. In some embodiments, an anti-reflective layer (not shown) is located on the back side of the first semiconductor substrate 104. In some embodiments, a passivation layer (not shown) is located on the anti-reflective layer. In some embodiments, a grid structure 452 is located above the DTI structure 450 and on the passivation layer. In some embodiments, a color filter 454 is located on the passivation layer. In some embodiments, a microlens 456 is located on the color filter 454.

[0047] In some embodiments, semiconductor substrates 104, 134, and 408 comprise silicon or other suitable materials. In some embodiments, transistors 114, 116, 136, 138, 140, 410, and 412 are metal-oxide-semiconductor field-effect transistors (MOSFETs), junction FETs, fin field-effect transistors (FFETs), gate all-around (GAA) FETs, or other suitable types of transistors. In some embodiments, source / drain electrodes 118, 120, 142, 144, 148, 150, 154, 156, 428, and 430 are doped regions of the semiconductor substrate. In some embodiments, gates 122, 146, 152, 158, and 432 comprise polycrystalline silicon, tungsten, tungsten nitride, titanium nitride, tantalum nitride, or other suitable gate electrode materials. In some embodiments, the dielectric layers of dielectric structures 124, 160, 182, and 414 comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide oxycarbide, hafnium oxide, or other suitable materials. In some embodiments, conductive interconnects 126, 162, 163, 416, 602, 604, 608, and 610 comprise copper, tungsten, aluminum, gold, silver, or other suitable materials. In some embodiments, conductive bonding pads 130, 166, 404, 426, 420, and 422 and conductive bonding contact windows 128, 164, 402, 424, and 418 comprise copper or other suitable materials. In some embodiments, BTSV 168 comprises copper, tungsten, or other suitable materials. In some embodiments, dielectric layer 434 comprises silicon oxide, silicon nitride, or other suitable materials. In some embodiments, dielectric layer 178 comprises silicon oxide, silicon nitride, or other suitable materials. In some embodiments, electrode layers 172, 176 comprise titanium nitride, tantalum nitride, or other suitable materials. In some embodiments, insulating layer 174 comprises a high-dielectric material (e.g., alumina, hafnium oxide, zirconium oxide, etc.) or other suitable materials.

[0048] Figures 9 to 31 illustrate cross-sectional views 900 to 3100 of a method for forming an image sensor integrated wafer including a LOFIC 170 in some embodiments, wherein the LOFIC 170 is formed along the back side 134b of a semiconductor substrate 134 and coupled to a pixel transistor 136 located on the front side 134a of the semiconductor substrate 134 via a BTSV 168 extending through the semiconductor substrate 134. Although Figures 9 to 31 are described with respect to one method, it should be understood that the structures disclosed in Figures 9 to 31 are not limited to this method and can exist as independent structures independent of this method.

[0049] As shown in cross-sectional view 900 of FIG9, pixels 106 and 108 are formed on the first semiconductor wafer 102. For example, photosensors 110 and 112 are formed in the first semiconductor substrate 104, and first transfer transistors 114 and 116 are formed along the first semiconductor substrate 104. Furthermore, dielectric structure 124, conductive interconnect 126, first conductive bonding contact window 128, and first conductive bonding pad 130 are formed on the front side of the first semiconductor substrate 104. Deep trench isolation (DTI) structure 450 extends from the back side of the first semiconductor substrate 104 into the first semiconductor substrate 104.

[0050] As shown in the cross-sectional view 1000 of Figure 10, pixel transistors 136, 138, and 140 are formed along the front side 134a of the second semiconductor substrate 134 of the second semiconductor wafer 132. Furthermore, dielectric structures 160, conductive interconnects 162 and 163, a second conductive bonding contact window 164, and a second conductive bonding pad 166 are formed on the front side 134a of the second semiconductor substrate 134.

[0051] As shown in cross-sectional view 1100 of FIG11, the second semiconductor wafer 132 and the first semiconductor wafer 102 are bonded together. For example, the second conductive bonding pad 166 and the first conductive bonding pad 130 are bonded together at the interface between the second semiconductor wafer 132 and the first semiconductor wafer 102. Furthermore, dielectric structure 160 and dielectric structure 124 are bonded together at this interface. In some embodiments, bonding includes a fusion bonding process, a direct bonding process, or other suitable processes.

[0052] As shown in the cross-sectional view 1200 of FIG12, the second semiconductor substrate 134 is thinned from its back side 134b. In some embodiments, thinning includes an etching process, a chemical mechanical planarization (CMP) process, or other suitable processes.

[0053] As shown in the cross-sectional view 1300 of FIG13, the dielectric layer 440 is deposited on the back side 134b of the second semiconductor substrate 134. In some embodiments, the dielectric layer 440 includes silicon oxide, silicon nitride or other suitable materials, and is deposited through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0054] As shown in the cross-sectional view 1400 of FIG14, the dielectric layer 440, the semiconductor substrate 134, and the dielectric structure 160 are etched to form a back-side substrate through-hole opening 1404. This etching extends from the back side 134b of the semiconductor substrate 134 through the front side 134a to the conductive interconnect 163. In some embodiments, the back-side substrate through-hole opening 1404 is defined by the sidewalls of the dielectric layer 440, the sidewalls of the semiconductor substrate 134, the sidewalls of the dielectric structure 160, and the lower surface of the conductive interconnect 163. In some embodiments, a masking layer 1402 is formed on the dielectric layer 440, and etching is performed according to the masking layer 1402. In some embodiments, the masking layer includes a photoresist material, a hard masking material, or other suitable material. In some embodiments, the etching includes a dry etching process, such as a plasma etching process, a reactive ion etching process, an ion beam etching process, or other suitable processes.

[0055] As shown in the cross-sectional view 1500 of FIG15, a dielectric layer 434 is deposited in the back-side substrate through-hole 1404 (e.g., on the sidewalls of dielectric layer 440, the sidewalls of semiconductor substrate 134, the sidewalls of dielectric structure 160, and the lower surface of conductive interconnect 163). The dielectric layer 434 liner the back-side substrate through-hole 1404 and fills a portion of the back-side substrate through-hole 1404. In some embodiments, the dielectric layer 434 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited through CVD, PVD, ALD, or other suitable processes. In some embodiments, the dielectric layer 434 is deposited while the masking layer 1402 still covers the dielectric layer 440.

[0056] As shown in the cross-sectional view 1600 of Figure 16, dielectric layer 434 is etched to expose the lower surface of conductive interconnect 163 at the bottom of the back-side substrate through-hole opening 1404. This etching removes a portion of dielectric layer 434 from the lower surface of conductive interconnect 163. In some embodiments, the etching extends slightly into the conductive interconnect 163. In some embodiments, a masking layer 1602 is formed over dielectric layers 440, 434, and the etching is performed according to the masking layer 1602. In some embodiments, the etching includes a dry etching process or other suitable process.

[0057] As shown in the cross-sectional view 1700 of FIG17, a back-side substrate via (BTSV) 168 is formed in the back-side substrate via opening 1404 (e.g., between the sidewalls of the dielectric layer 434) and on the lower surface of the conductive interconnect 163. In some embodiments, forming a BTSV includes depositing a conductive resistance barrier layer in the back-side substrate via opening 1404 and depositing a conductive fill layer on top of the conductive resistance barrier layer to fill the back-side substrate via opening 1404. In some embodiments, the BTSV 168 comprises copper, tungsten, aluminum, or other suitable materials and is deposited through CVD, PVD, ALD, sputtering, electrochemical plating (ECP), electroless deposition (ELD), or other suitable processes. In some embodiments, after depositing the BTSV 168 layer, a planarization process (e.g., CMP process or other suitable process) is performed on the BTSV 168 and dielectric layer 440 to further define the BTSV 168.

[0058] As shown in the cross-sectional view 1800 of Figure 18, dielectric layer 442 is deposited on dielectric layer 440, dielectric layer 434, and BTSV 168. In some embodiments, dielectric layer 442 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited through CVD, PVD, ALD, or other suitable processes.

[0059] As shown in the cross-sectional view 1900 of FIG19, dielectric layer 442, dielectric layer 440, and semiconductor substrate 134 are etched to form a capacitor trench 1904 in the back side 134b of semiconductor substrate 134. This etching extends from the back side 134b of semiconductor substrate 134 into the semiconductor substrate 134 located above pixel transistors 136, 138, and 140. The capacitor trench 1904 is defined by the sidewalls of dielectric layer 442, the sidewalls of dielectric layer 440, the sidewalls of semiconductor substrate 134, and the lower surface of semiconductor substrate 134. In some embodiments, a mask layer 1902 is formed on dielectric layer 442, and the etching is performed according to the mask layer 1902. In some embodiments, the etching includes a dry etching process, a wet etching process, or other suitable processes.

[0060] As shown in the cross-sectional view 2000 of FIG20, a dielectric layer 178 is deposited in a capacitor trench 1904 (e.g., on the sidewalls of dielectric layer 442, the sidewalls of dielectric layer 440, the sidewalls of semiconductor substrate 134, and the lower surface of semiconductor substrate 134). The dielectric layer 178 liner the capacitor trench 1904 and fills a portion of the capacitor trench 1904. In some embodiments, the dielectric layer 178 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited through a CVD process, a PVD process, an ALD process, or other suitable process. In some embodiments, the dielectric layer 178 is deposited while the masking layer 1902 still covers the dielectric layer 442.

[0061] As shown in cross-sectional view 2100 of Figure 21, a lateral overflow integrating capacitor (LOFIC) 170 is formed along the back side 134b of the semiconductor substrate 134 and in a capacitor trench 1904. A first electrode layer 172 of the LOFIC 170 is deposited in the capacitor trench 1904, on the dielectric layer 178, and on the dielectric layer 442. An insulating layer 174 of the LOFIC 170 is deposited in the capacitor trench 1904 and on the first electrode layer 172. A second electrode layer 176 of the LOFIC 170 is deposited in the capacitor trench 1904 and on the insulating layer 174. The second electrode layer 176 fills the capacitor trench 1904. In some embodiments, the first electrode layer 172 and / or the second electrode layer 176 comprise titanium nitride or other suitable materials and are deposited through CVD, PVD, ALD, sputtering, ECP, ELD, or other suitable processes. In some embodiments, the insulating layer 174 comprises a high-dielectric material (e.g., alumina, hafnium oxide, zirconium oxide, or the like) or other suitable material, and is deposited through a CVD process, a PVD process, an ALD process, or other suitable process.

[0062] As shown in the cross-sectional view 2200 of FIG22, the second electrode layer 176 and the insulating layer 174 are etched to further define the second electrode layer 176 and the insulating layer 174. In some embodiments, a masking layer 2202 is formed on the second electrode layer 176, and etching is performed according to the masking layer 2202. In some embodiments, etching includes a dry etching process or other suitable processes.

[0063] Figures 23 to 26 illustrate cross-sectional views 2300 to 2600 of a method for coupling the first electrode layer 172 to the BTSV 168 in some embodiments.

[0064] As shown in the cross-sectional view 2300 of Figure 23, the first electrode layer 172 is etched to further define the first electrode layer 172. After etching, the first electrode layer 172 remains directly above the BTSV 168. In some embodiments, a mask layer 2302 is formed over the second electrode layer 176 and the first electrode layer 172, and etching is performed based on the mask layer 2302. In some embodiments, etching includes a dry etching process or other suitable processes.

[0065] As shown in cross-sectional view 2400 of Figure 24, a dielectric layer 444 is deposited on the first electrode layer 172 and the second electrode layer 176. Furthermore, a planarization process is performed on the dielectric layer 444 and the second electrode layer 176. In some embodiments, the dielectric layer 444 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited through a CVD process, a PVD process, an ALD process, or other suitable process. In some embodiments, the planarization process is or includes a CMP process or other suitable process.

[0066] As shown in cross-sectional view 2500 of Figure 25, dielectric layer 446 is deposited over dielectric layer 444 and second electrode layer 176. Furthermore, dielectric layer 446 is etched to form openings 2504 and 2506 therein. Additionally, dielectric layer 446, dielectric layer 444, first electrode layer 172, and dielectric layer 442 are etched to form openings 2508 and 2510 therein. Openings 2504 and 2506 expose a portion of the second electrode layer 176. Openings 2508 and 2510 expose a portion of the lower surface of the BTSV and a portion of the first electrode layer 172 (e.g., the sidewalls of the first electrode layer 172). Opening 2508 is defined by the sidewalls of dielectric layer 446, dielectric layer 444, the first electrode layer 172, the sidewalls of dielectric layer 442, and the lower surface of the BTSV 168.

[0067] In some embodiments, dielectric layer 446 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited via CVD, PVD, ALD, or other suitable processes. In some embodiments, one or more masking layers (e.g., masking layer 2502) are formed over dielectric layer 446, and etching is performed based on the masking layers. In some embodiments, etching includes dry etching or other suitable processes. In some embodiments, openings 2504 and 2508 are formed via a first etching process and a first masking layer, and openings 2506 and 2510 are formed via a second etching process and a second masking layer. In some embodiments, etching extends slightly into the second electrode layer 176 and / or slightly into BTSV 168.

[0068] As shown in cross-sectional view 2600 of Figure 26, a back-side conductive bonding contact window 424 and a back-side conductive bonding pad 426 are formed in openings 2504 and 2506, respectively. Furthermore, a back-side conductive bonding contact window 402 and a back-side conductive bonding pad 404 are formed in openings 2508 and 2510, respectively. In some embodiments, forming the back-side conductive bonding contact windows 402, 424 and the back-side conductive bonding pads 404, 426 includes depositing a conductive resistance barrier layer in openings 2504, 2506, 2508, and 2510, and depositing a conductive fill layer on top of the conductive resistance barrier layer to fill the openings. In some embodiments, the back-side conductive bonding contact windows 402, 424 and the back-side conductive bonding pads 404, 426 comprise copper, tungsten, aluminum, or other suitable materials, and are deposited through CVD, PVD, ALD, sputtering, ECP, ELD, or other suitable processes. In some embodiments, a planarization process (e.g., CMP process or other suitable process) is performed on the back-side conductive bonding pads 404, 426 and dielectric layer 446 after deposition.

[0069] As shown in the cross-sectional view 2700 of Figure 27, transistors 410 and 412 are formed on the front side of the third semiconductor substrate 408 of the third semiconductor wafer. In addition, dielectric structure 414, conductive interconnect 416, conductive bonding contact window 418, and conductive bonding pads 420 and 422 are formed on the front side of the third semiconductor substrate 408.

[0070] Next, the third semiconductor wafer 406 and the second semiconductor wafer 132 are bonded together. For example, back-side conductive bonding pad 404 and conductive bonding pad 422 are bonded together at the interface between the second semiconductor wafer 132 and the third semiconductor wafer 406. Furthermore, back-side conductive bonding pad 426 and conductive bonding pad 420 are bonded together at the interface between the second semiconductor wafer 132 and the third semiconductor wafer 406. Additionally, dielectric structure 182 and dielectric structure 414 are bonded together at the interface. In some embodiments, bonding includes a fusion bonding process, a direct bonding process, or other suitable processes.

[0071] In some embodiments, an anti-reflective layer (not shown) is formed along the back side of the first semiconductor substrate 104. In some embodiments, a passivation layer (not shown) is formed on the anti-reflective layer. In some embodiments, a grid structure 452 is formed on the DTI structure 450 and the passivation layer. In some embodiments, a color filter 454 is formed on the passivation layer. In some embodiments, a microlens 456 is formed on the color filter 454.

[0072] Figures 28 to 32 are cross-sectional views 2800 to 3200 illustrating a method for coupling the first electrode layer 172 to the BTSV 168 in some other embodiments.

[0073] As shown in the cross-sectional view 2800 of Figure 28, the first electrode layer 172 is etched to further define the first electrode layer 172. The etching removes the first electrode layer 172 directly above the BTSV 168. In some embodiments, a mask layer 2802 is formed over the second electrode layer 176 and the first electrode layer 172, and etching is performed based on the mask layer 2802. In some embodiments, the etching includes a dry etching process or other suitable process.

[0074] As shown in the cross-sectional view 2900 of Figure 29, dielectric layer 444 is deposited on the first electrode layer 172 and the second electrode layer 176. Dielectric layer 2902 is deposited on dielectric layer 444. In some embodiments, dielectric layer 2902 comprises silicon oxide, silicon nitride, or other suitable materials and is deposited through chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0075] A back-side conductive via 602 is formed on BTSV 168. A back-side conductive via 606 is formed on the first electrode layer 172. A back-side conductive via 608 is formed on the second electrode layer 176. A back-side conductive interconnect 604 is formed on the back-side conductive vias 602 and 606. A back-side conductive interconnect 610 is formed on the back-side conductive via 608. In some embodiments, the back-side conductive vias 602, 606, 608 and the back-side conductive interconnects 604, 610 comprise copper, aluminum, tungsten or other suitable materials and are deposited through one or more chemical vapor deposition processes, physical vapor deposition processes, atomic layer deposition processes, electrochemical plating processes, electroless plating deposition processes or other suitable processes.

[0076] As shown in the cross-sectional view 3000 of Figure 30, dielectric layer 446 is deposited on dielectric layer 2902. In addition, back-side conductive bonding contact window 424 is formed on back-side conductive interconnect 610, and back-side conductive bonding pad 426 is formed on back-side conductive bonding contact window 424.

[0077] As shown in the cross-sectional view 3100 of Figure 31, the third semiconductor wafer 406 and the second semiconductor wafer 132 are bonded together.

[0078] Figure 32 illustrates a flowchart of a method 3200 for forming an image sensor integrated wafer including a LOFIC along the back side of a semiconductor substrate and coupled to a pixel transistor along the front side of the semiconductor substrate via a BTSV extending through the semiconductor substrate. While method 3200 is illustrated and described as a series of steps or events, it should be understood that the order of the illustrated steps or events should not be construed as limiting. For example, some steps may occur in a different order than those shown and / or described, and / or simultaneously with other steps or events. Furthermore, not all illustrated steps may require the implementation of one or more aspects or embodiments described herein. Moreover, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0079] In block 3202, a photosensor and a transfer transistor are formed along the first semiconductor substrate of the first semiconductor wafer. Figure 9 illustrates a cross-sectional view 900 corresponding to some embodiments of block 3202.

[0080] In block 3204, pixel transistors are formed along the front side of the second semiconductor substrate of the second semiconductor wafer. Figure 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of block 3204.

[0081] In block 3206, a first conductive interconnect is formed on the second semiconductor wafer and coupled to the pixel transistor. Figure 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of block 3206.

[0082] In block 3208, the second semiconductor wafer and the first semiconductor wafer are bonded together, so that the pixel transistor is coupled to the transfer transistor. Figure 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of block 3208.

[0083] In block 3210, a back-side substrate through-hole (BTSV) is formed, extending from the back side through the front side, through the second semiconductor substrate, to the first conductive interconnect. Figures 14 to 17 illustrate cross-sectional views 1400 to 1700 of some embodiments corresponding to block 3210.

[0084] In block 3212, a lateral overflow integral capacitor (LOFIC) is formed along the back side of the second semiconductor substrate and coupled to the BTSV. Figures 19 to 26 illustrate cross-sectional views 1900 to 2600 of some embodiments corresponding to block 3212. Figures 19 to 22 and Figures 28 to 30 illustrate cross-sectional views 1900 to 2600 and cross-sectional views 2800 to 3000 of some other embodiments corresponding to block 3212.

[0085] In block 3214, a reference transistor is formed along the third semiconductor substrate of the third semiconductor wafer. Figure 27 illustrates a cross-sectional view 2700 corresponding to some embodiments of block 3214. Figure 31 illustrates a cross-sectional view 3100 corresponding to some other embodiments of block 3214.

[0086] In block 3216, the third semiconductor wafer and the second semiconductor wafer are bonded together, and the reference transistor is coupled to the LOFIC. Figure 27 illustrates a cross-sectional view 2700 corresponding to some embodiments of block 3216. Figure 31 illustrates a cross-sectional view 3100 corresponding to some other embodiments of block 3216.

[0087] Therefore, this disclosure relates to an image sensor integrated chip containing a LOFIC that runs along the back side of a semiconductor substrate and is coupled to a pixel transistor running along the front side of the semiconductor substrate via a BTSV extending through the semiconductor substrate.

[0088] Therefore, in some embodiments, this disclosure relates to an integrated wafer including a first transistor along the front side of a first semiconductor substrate. The first transistor includes a first source / drain, a second source / drain, and a gate. A first conductive interconnect is located on the front side of the first semiconductor substrate and coupled to the second source / drain of the first transistor. A back-side substrate via (BTSV) extends from the back side of the first semiconductor substrate through the front side of the first semiconductor substrate to the first conductive interconnect. A capacitor extends along and into the first semiconductor substrate from the back side of the first semiconductor substrate. The capacitor includes a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. The first electrode layer is coupled to the second source / drain of the first transistor through the BTSV and the first conductive interconnect.

[0089] In other embodiments, this disclosure relates to an integrated wafer of a photosensor included in a first semiconductor substrate of a first semiconductor wafer. A transfer transistor runs along the first semiconductor substrate. The transfer transistor includes a first source / drain coupled to the photosensor. A first pixel transistor runs along the front side of a second semiconductor substrate bonded to a second semiconductor wafer of the first semiconductor wafer. The first pixel transistor includes a first source / drain coupled to a second source / drain of the transfer transistor via a first conductive bonding pad and a second conductive bonding pad bonded together at an interface between the first and second semiconductor wafers. A back-side substrate via (BTSV) extends from the back side of the second semiconductor substrate through the front side of the second semiconductor substrate. The BTSV is coupled to the second source / drain of the first pixel transistor via a first conductive interconnect on the second semiconductor wafer. A lateral overflow integrating capacitor (LOFIC) runs along the back side of the second semiconductor substrate. The LOFIC includes a first electrode layer coupled to the BTSV and extending along the back side of the second semiconductor substrate and between the sidewalls of the second semiconductor substrate. The LOFIC includes a second electrode layer extending along the back side of the second semiconductor substrate, between the sidewalls of the second semiconductor substrate, and between the sidewalls of the first electrode layer. The LOFIC includes an insulating layer between the first electrode layer and the second electrode layer.

[0090] In other embodiments, this disclosure relates to a method of forming an integrated wafer. The method includes forming a first transistor along the front side of a first semiconductor substrate of a first semiconductor wafer. The first transistor includes a first source / drain, a second source / drain, and a gate. The method includes forming a first conductive interconnect coupled to a second source / drain of the first transistor on the front side of the first semiconductor substrate. The method includes etching the first semiconductor substrate from a back side to a front side to form a through-substrate via extending from the back side through the front side of the first semiconductor substrate and exposing a portion of the first conductive interconnect. The method includes depositing a conductive layer from the back side of the first semiconductor substrate in the through-substrate via and on a portion of the first conductive interconnect to form a back-side substrate via (BTSV). The method includes etching the first semiconductor substrate from a back side to a front side to form a capacitor trench in the first semiconductor substrate. The method includes depositing a first electrode layer, an insulating layer, and a second electrode layer in the capacitor trench and along the back side of the first semiconductor substrate to form a capacitor in the capacitor trench and along the back side of the first semiconductor substrate. The first electrode layer is coupled to the second source / drain of the first transistor through BTSV and the first conductive interconnect.

[0091] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0092] 100, 300, 400, 600 to 3100: Sectional View 102: First Semiconductor Wafer 104: First Semiconductor Substrate 106: First pixel 108: Second pixel 110: Light sensor 112: Second light sensor 114: First transfer transistor 116: Second transfer transistor 118, 142, 148, 154, 428: First source / drain electrode 120, 144, 150, 156, 430: Second source / drain electrode 122, 146, 152, 158, 432: Gate 124: First dielectric structure 126, 162, 163, 416: Conductive internal wiring 128: First conductive bonding contact window 130: First conductive bonding pad 132: Second semiconductor wafer 134: Semiconductor substrate 134a: Anterior side 134b: Dorsal side 134c: First sidewall 134d: Second sidewall 134e, 172f: Lower surface 136: First pixel transistor 138: Second pixel transistor 140: Third pixel transistor 160: Second dielectric structure 164: Second conductive bonding contact window 166: Second conductive bonding pad 168: Through-the-back substrate (BTSV) 170: Lateral Overflow Integrating Capacitor (LOFIC) 172: First electrode layer 172a, 172b: Lateral wall 172d, 172e: Inner wall 172g, 176a, 176b: Sidewall 172c, 176c: Upper surface 174: Insulation layer 176: Second electrode layer 178, 434, 440, 442, 444, 446, 2902: Dielectric layer 180: line 182: Backside dielectric structure, dielectric structure 200: Circuit Diagram 202, 206, 212, 218, 224, 232, 238: First terminal 204, 208, 214, 220, 226, 234, 240: Second terminals 210, 216, 222, 228, 236: Control terminals 230: Fourth pixel transistor 242: Reference voltage terminal 250: Power supply voltage terminal 252: Output terminal 402, 424: Backside conductive bonding contact window 404, 426: Backside conductive bonding pads 406: Third Semiconductor Wafer 408: Third semiconductor substrate 410: Reference transistor 412, 414: Transistors 418: Conductive bonding contact window 420, 422: Conductive bonding pads 436, 438: Dashed lines 448: Shallow Trench Isolation (STI) Structure 450: Deep Trench Isolation (DTI) Structure 452: Grid structure 454: Color Filter 456: Microlenses 500: Top View 602, 606: Backside conductive vias 604, 608, 610: Backside conductive internal interconnects 1402, 1602, 1902, 2202, 2302, 2502, 2802: Masking layer 1404: Backside substrate through-hole opening 1904: Capacitor trench 2504, 2506, 2508, 2510: Opening 3200: Method Blocks 3202, 3204, 3206, 3208, 3210, 3212, 3214, and 3216 A-A': line

Claims

1. An integrated chip, comprising: A first transistor along the front side of a first semiconductor substrate, the first transistor including a first source / drain, a second source / drain and a gate; A first conductive interconnect on the front side of the first semiconductor substrate, coupled to the second source / drain of the first transistor; a back-side substrate via (BTSV) extending from the back side of the first semiconductor substrate through the front side of the first semiconductor substrate to the first conductive interconnect; and a capacitor along the back side of the first semiconductor substrate, extending from the back side of the first semiconductor substrate into the first semiconductor substrate below the first transistor without reaching the front side of the first semiconductor substrate, the capacitor including a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer, wherein the first electrode layer is coupled to the second source / drain of the first transistor through the back-side substrate via and the first conductive interconnect.

2. The integrated wafer as described in claim 1, further comprising: A photosensitive sensor in a second semiconductor substrate and a transfer transistor along the second semiconductor substrate, the transfer transistor including a first source / drain coupled to the photosensitive sensor, the transfer transistor including a second source / drain coupled to the first source / drain of the first transistor; and a second transistor along the front side of the first semiconductor substrate, the second transistor including a gate coupled to the first source / drain of the first transistor and the second source / drain of the transfer transistor.

3. The integrated wafer as described in claim 1, further comprising: A first back-side conductive bonding contact window and a first back-side conductive bonding pad are provided on the back side of the first semiconductor substrate. The first back-side conductive bonding contact window extends from the first back-side conductive bonding pad through the first electrode layer to the back-side substrate through-hole and couples the first electrode layer to the back-side substrate through-hole.

4. The integrated wafer as claimed in claim 3, wherein the first back-side conductive bonding contact window directly contacts the sidewall of the first electrode layer and the lower surface of the back-side substrate through-hole.

5. The integrated wafer as described in claim 3, further comprising: A second back-side conductive bonding contact window and a second back-side conductive bonding pad are provided on the back side of the first semiconductor substrate. The second back-side conductive bonding contact window extends from the second back-side conductive bonding pad to the second electrode layer and couples the second back-side conductive bonding pad to the second electrode layer.

6. The integrated wafer as described in claim 3, further comprising: A second conductive bonding pad is bonded and coupled to the first back-side conductive bonding pad, wherein the first back-side conductive bonding pad is located directly between the first back-side conductive bonding contact window and the second conductive bonding pad.

7. An integrated chip, comprising: A photosensor in the first semiconductor substrate of the first semiconductor wafer; A transfer transistor along the first semiconductor substrate, the transfer transistor including a first source / drain coupled to the photosensor; a first pixel transistor along the front side of the second semiconductor substrate of the second semiconductor wafer, the second semiconductor wafer being bonded to the first semiconductor wafer, the first pixel transistor including a first source / drain coupled to the second source / drain of the transfer transistor via a first conductive bonding pad and a second conductive bonding pad, the first conductive bonding pad and the second conductive bonding pad being bonded together at the interface between the first semiconductor wafer and the second semiconductor wafer; A back-side substrate through-hole (BTSV) extends from the back side of the second semiconductor substrate through the front side of the second semiconductor substrate, wherein the BTSV is coupled to the second source / drain of the first pixel transistor through a first conductive interconnect on the second semiconductor wafer; and a lateral overflow integral capacitor (LOFIC) along the back side of the second semiconductor substrate, the LOFIC including a first electrode layer, a second electrode layer and an insulating layer, the first electrode layer being coupled to the BTSV and extending along the back side of the second semiconductor substrate and located between the sidewalls of the second semiconductor substrate, the second electrode layer extending along the back side of the second semiconductor substrate and located between the sidewalls of the second semiconductor substrate and between the sidewalls of the first electrode layer, the insulating layer being located between the first electrode layer and the second electrode layer, wherein the LOFIC extends from the back side of the second semiconductor substrate into the second semiconductor substrate below the first pixel transistor without reaching the front side of the second semiconductor substrate.

8. The integrated wafer as described in claim 7, further comprising: A reference transistor along a third semiconductor substrate of a third semiconductor wafer, the third semiconductor wafer being bonded to a second semiconductor wafer, the reference transistor including a first source / drain, coupled to a second electrode layer via a third conductive bonding pad and a fourth conductive bonding pad, the third conductive bonding pad and the fourth conductive bonding pad being bonded together at the interface between the second semiconductor wafer and the third semiconductor wafer, the reference transistor including a second source / drain coupled to a reference voltage terminal.

9. A method for forming an integrated wafer, the method comprising: A first transistor is formed along the front side of a first semiconductor substrate of a first semiconductor wafer. The first transistor includes a first source / drain, a second source / drain, and a gate. A first conductive interconnect is formed on the front side of the first semiconductor substrate and coupled to the second source / drain of the first transistor; the first semiconductor substrate is etched from the back side toward the front side to form a substrate through-hole opening, the substrate through-hole opening passing through the front side of the first semiconductor substrate from the back side and exposing a portion of the first conductive interconnect; a conductive layer is deposited from the back side of the first semiconductor substrate on the substrate through-hole opening and the portion of the first conductive interconnect to form a back-side substrate through-hole (BTSV); the first semiconductor substrate is etched from the back side toward the front side to form a capacitor trench in the first semiconductor substrate; and a first electrode layer, an insulating layer, and a second electrode layer are deposited in the capacitor trench and along the back side of the first semiconductor substrate to form a capacitor in the capacitor trench and along the back side of the first semiconductor substrate, wherein the first electrode layer is coupled to the second source / drain of the first transistor through the back-side substrate through-hole and the first conductive interconnect. The capacitor extends along the back side of the first semiconductor substrate and from the back side of the first semiconductor substrate into the first semiconductor substrate below the first transistor, without reaching the front side of the first semiconductor substrate.

10. The method as described in claim 9, further comprising: A photosensor is formed in a second semiconductor substrate, and a transfer transistor is formed along the second semiconductor substrate of a second semiconductor wafer, the transfer transistor including a first source / drain coupled to the photosensor; the second semiconductor wafer and the first semiconductor wafer are bonded together such that a second source / drain of the transfer transistor is coupled to the first source / drain of the first transistor; a second transistor is formed along the third semiconductor substrate of a third semiconductor wafer, the second transistor including a first source / drain coupled to a reference voltage terminal; and the third semiconductor wafer and the first semiconductor wafer are bonded together such that a second source / drain of the second transistor is coupled to the second electrode layer.

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