Semiconductor device and method of making the same

Abstract

In some embodiments, a method is described that includes forming a first electrically conductive material in first opening of a first masking structure to provide a first conductive line, and forming a second electrically conductive material in second opening of a second masking structure to provide a conductive via. The second masking structure may be removed, and a dielectric layer is formed covering the first conductive line and the conductive via. The method may further include planarizing the dielectric layer to expose an upper surface of the conductive via, and forming an under-bump metallurgy on the planarized surface of the conductive via. The under-bump metallurgy may include a seed layer that covers an interface between the under-bump metallurgy and the conductive via.

Description

Technical Field

[0001] The embodiments disclosed herein relate to semiconductor devices and methods of manufacturing the same. Prior Technology

[0002] Since the invention of integrated circuits (ICs), the semiconductor industry has developed rapidly due to the continuous increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, the increase in integration density stems from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. In order to further improve circuit density, people have begun to study three-dimensional (3D) integrated circuits.

[0003] In some packaging technologies, the integrated circuit die is discretely separated from the wafer before packaging. One advantage of this technology is the ability to create fan-out packages, which allows the I / O pads on the die to be redistributed over a larger area. This increases the number of I / O pads on the die surface. Summary of the Invention

[0004] This disclosure discloses a method for manufacturing a semiconductor device, comprising: forming a first conductive material in a first opening of a first mask structure to provide a first conductive wire; forming a second conductive material in a second opening of a second mask structure to provide a via on the first conductive wire; removing the second mask structure; forming a dielectric layer covering the first conductive wire and the via; planarizing the dielectric layer to expose an upper surface of the via, wherein after planarization, the upper surface of the via is recessed relative to the upper surface of the dielectric layer; and forming a conductive feature including a seed layer on top of the upper surface of the via, wherein the seed layer covers the upper surface of the via and the upper surface of the dielectric layer.

[0005] This disclosure discloses a method for manufacturing a semiconductor device, comprising: forming a redistributed circuit structure, including: forming a first via in a first opening of a first mask structure; removing the first mask structure; forming a first dielectric layer covering the first via; planarizing the first dielectric layer to expose an upper surface of the first via; forming an under-bump metal, including a first seed layer on top of the upper surface of the first via, wherein the first seed layer of the under-bump metal completely covers a first interface between the under-bump metal and the first via; and attaching a module socket to the under-bump metal of the redistributed circuit structure.

[0006] This disclosure discloses a semiconductor device comprising: a redistributed wiring structure including: a via extending through a dielectric layer to a first conductor, wherein an upper surface of the via is recessed relative to an upper surface of the dielectric layer, and wherein the height difference between the upper surface of the via and the upper surface of the dielectric layer is not greater than 0.15 micrometers; and an under-bump metal including a seed layer located on top of the upper surface of the via and the upper surface of the dielectric layer, wherein the seed layer completely covers the interface between the under-bump metal and the upper surface of the via, the interface having no gaps; and a module socket connected to the under-bump metal. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 shows a cross-sectional view of an integrated circuit die according to some embodiments.

[0009] Figures 2 through 5F and Figures 6 through 11 show various views of intermediate steps during the process of forming a packaged assembly according to some embodiments.

[0010] Figure 5G is a perspective view showing a gapless interface between a conductor and a via according to some embodiments.

[0011] Figures 12 and 13 show various views of the process of securing the packaged components between the thermal module and the mechanical support according to some embodiments.

[0012] Figure 14 illustrates a system-on-a-wafer assembly obtained using packaging components according to various embodiments. Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, an indication of a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatially relative terms such as "below," "under," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figure and another. Spatially relative terms are intended to cover different orientations of the device during use or operation besides those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0015] According to various embodiments, vias and overlay conductors in a fan-out redistribution circuit structure are formed with a high-quality interface for use in electrical device packaging. Even if the interface between the upper surface of the via and the overlay conductor is recessed, voids at the upper surface of the via can be eliminated (or at least significantly reduced). In some embodiments, the methods and structures described herein can reduce the recess of the upper surface of the via and increase the step coverage of the seed layer of the overlay conductor, thus greatly reducing and / or eliminating the possibility of voids forming between the conductor and the via.

[0016] Figure 1 shows a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or an application-specific die (e.g., an application-specific integrated circuit). Circuits, ASICs, field-programmable gate arrays (FPGAs), etc., or combinations thereof.

[0017] Integrated circuit dies 50 can be formed in a wafer and may include different device regions that are monomerized in subsequent steps to form multiple integrated circuit dies. Integrated circuit dies 50 can be fabricated according to applicable manufacturing processes to form integrated circuits. For example, integrated circuit dies 50 include a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Semiconductor substrate 52 has an active surface (e.g., the upward-facing surface in FIG. 1), sometimes referred to as the front side, and an inactive surface (e.g., the downward-facing surface in FIG. 1), sometimes referred to as the back side. Multiple devices may be formed on the front surface of semiconductor substrate 52. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Interconnect structures are located on semiconductor substrate 52 and interconnect the multiple devices to form an integrated circuit. The interconnect structures may be formed from, for example, multiple metallization patterns in multiple dielectric layers on semiconductor substrate 52. The multiple metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The multiple metallization patterns of the interconnect structures are electrically coupled to the multiple devices on semiconductor substrate 52.

[0018] The integrated circuit die 50 also includes a plurality of pads 62, such as aluminum pads, for external connection. The plurality of pads 62 are located on the active side of the integrated circuit die 50, for example, within and / or on an interconnect structure. One or more passivation films 64 are located on the integrated circuit die 50, for example, on portions of the interconnect structure and on portions of the plurality of pads 62. A plurality of openings extend through the plurality of passivation films 64 to the plurality of pads 62. A plurality of die connectors 66 (e.g., conductive pillars) (e.g., formed of a metal such as copper) extend through the plurality of openings in the plurality of passivation films 64 and are physically and electrically coupled to corresponding ones of the plurality of pads 62. The plurality of die connectors 66 may be formed, for example, through plating or the like. The plurality of die connectors 66 are electrically coupled to corresponding integrated circuits of the integrated circuit die 50.

[0019] Optionally, multiple solder regions (e.g., solder balls or solder bumps) can be configured on multiple pads 62. Solder balls can be used for chip probe (CP) testing of the integrated circuit die 50. CP testing of the integrated circuit die 50 can determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit dies 50 that have undergone subsequent processing (belonging to KGD) are packaged, while dies that fail the CP test are not packaged. After testing, the solder regions can be removed in subsequent processing steps.

[0020] The dielectric layer 68 may (or may not) be located on the active side of the integrated circuit die 50, for example, on the plurality of passivation films 64 and the plurality of die connectors 66. The dielectric layer 68 laterally encapsulates the plurality of die connectors 66 and is laterally adjacent to the integrated circuit die 50. Initially, the dielectric layer 68 may bury the plurality of die connectors 66 such that the topmost surface of the dielectric layer 68 is above the topmost surface of the plurality of die connectors 66. In some embodiments where solder regions are disposed on the die connectors 66, the dielectric layer 68 may also bury the solder regions. Alternatively, the solder regions may be removed before the dielectric layer 68 is formed.

[0021] The dielectric layer 68 can be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or a combination thereof. The dielectric layer 68 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the integrated circuit die 50, a plurality of die connectors 66 are exposed through the dielectric layer 68. In some embodiments, the plurality of die connectors 66 remain buried and are exposed in subsequent processes for packaging the integrated circuit die 50. Exposing multiple die connectors 66 may remove any solder areas that may be present on the multiple die connectors 66.

[0022] In some embodiments, the integrated circuit die 50 is a stacked device comprising a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device comprising a plurality of memory dies, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, etc. In such embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected through a plurality of through-substrate vias (TSVs). Each semiconductor substrate 52 may have (or may not have) an interconnect structure.

[0023] Figures 2 through 11 show various views of intermediate steps during the fabrication process of forming package assembly 100 according to some embodiments. Figures 2, 3, 4, 5A, 5B, 5C, 5D, 5F, 6, 7, 8, 9, 11, 13, and 14 are cross-sectional views. Figures 5E and 10 are top views. Figure 12 is a cross-sectional view. Figure 5G is a microscopic image. Package assembly 100 is a reconstructed wafer having multiple package regions, each package region encapsulating one or more integrated circuit dies 50. The multiple package regions include multiple computing stations 101 and multiple connection stations 102. Each computing station 101 may have, for example, logic functions, storage functions, etc., and package assembly 100 may be a single computing device including multiple computing stations 101 and multiple connection stations 102, such as a system-on-wafer (SoW) device. For example, the package component 100 can be an artificial intelligence (AI) accelerator, and each computing station 101 can be a neural network node of the AI ​​accelerator. Each connection station 102 can have, for example, an external connector, and the multiple computing stations 101 of the package component 100 can be connected to external systems through multiple stations 102. Exemplary systems of the package component 100 include AI servers, high-performance computing (HPC) systems, high-power computing devices, cloud computing systems, edge computing systems, etc. Two computing stations 101 (e.g., computing stations 101A and 101B) and one connection station 102 (e.g., connection station 102A) are shown, but it should be understood that the package component 100 can include many computing stations 101 and connection stations 102, and the stations can be arranged in various ways. Figure 10 illustrates and discusses an exemplary layout of the package component 100. Figures 2, 3, 4, 6, 7, 8, 9 and 11 show only a portion of the encapsulation assembly 100, such as the cross-section AA in Figure 10.

[0024] Multiple devices in the package assembly 100 are interconnected via a redistribution structure. Multiple conductive features of the redistribution structure may have gapless interfaces. Figure 5G is a perspective view showing a gapless interface between conductors and vias. A gapless interface can be formed by minimizing the depth of the recess on the upper surface of the vias. The recess on the upper surface of the multiple vias can be minimized by forming multiple vias, backfilling a dielectric layer to cover the multiple vias, planarizing the backfilled dielectric layer and the upper surfaces of the multiple vias, and then forming multiple conductors on the planarized multiple vias.

[0025] Figure 2 shows a carrier substrate 103, on which an adhesive layer 104 is formed. The carrier substrate 103 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 103 can be a wafer, allowing multiple packages to be formed simultaneously on the carrier substrate 103. The adhesive layer 104 may be removed along with the carrier substrate 103 from the overlay structure formed in subsequent steps. In some embodiments, the adhesive layer 104 is any suitable adhesive, epoxy resin, die attach film (DAF), etc., and is applied to the surface of the carrier substrate 103.

[0026] Multiple integrated circuit dies 50 are then attached to the adhesive layer 104. The desired type and number of integrated circuit dies 50 are attached to each computing site 101A, 101B, and connection site 102A, respectively. In some embodiments, a first type of integrated circuit die (e.g., SoC die 50A) is attached to each computing site 101A and 101B, and a second type of integrated circuit die (e.g., I / O interface die 50B) is attached to the connection site 102A. Although a single integrated circuit die 50 is shown for each site, it should be understood that multiple integrated circuit dies can be attached adjacent to each other in some or all sites. When multiple integrated circuit dies are attached to each computing site 101A and 101B, they can be of the same technology node or different technology nodes. For example, the integrated circuit die 50 may include dies formed at a 10 nm technology node, dies formed at a 7 nm technology node, or combinations thereof.

[0027] In Figure 3, encapsulations 96 are formed on and around each component. After formation, the encapsulations 96 encapsulate multiple integrated circuit chips 50. The encapsulations 96 can be molding compounds, epoxy resins, etc., and can be applied by compression molding, transfer molding, or other methods. The encapsulations 96 can be applied in liquid or semi-liquid form and then cured. In some embodiments, the encapsulations 96 are formed on a carrier substrate 103 such that multiple integrated circuit chips 50 are buried or covered, and then a planarization process is performed on the encapsulations 96 to expose multiple die connectors 66 of the multiple integrated circuit chips 50. After the planarization process, the top surfaces of the encapsulations 96, the multiple die connectors 66, and the dielectric layer 68 are coplanar. The planarization process can be, for example, chemical-mechanical polishing (CMP).

[0028] In Figure 4, a redistribution structure 108 is formed on the encapsulation 96 and multiple integrated circuit dies 50. The redistribution structure 108 includes multiple metallization patterns and multiple dielectric layers. The metallization patterns can also be referred to as redistribution layers or redistribution routes. Taking the redistribution structure 108 as an example, it has six metallization patterns. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 108. If fewer dielectric layers and metallization patterns are required, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are required, the steps and processes discussed below can be repeated. In this example, the redistribution structure 108 includes dielectric layers 110, 114, 118, 122, 126, 130, and 134, and also includes metallization patterns 112, 116, 120, 124, 128, and 132. Metallization patterns 112, 116, 120, 124, 128, and 132 may include horizontally oriented conductors and vertically oriented vias.

[0029] Figures 5A to 5F illustrate some embodiments of forming multiple layers of the redistributed circuit structure 108 shown in Figure 4. Specifically, processes for forming multiple metallization patterns and multiple dielectric layers are shown. Each metallization pattern includes multiple vias and multiple conductors overlying the vias. The multiple metallization patterns of the redistributed circuit structure 108 are formed using a process that creates a high-quality interface between the upper surfaces of the multiple vias and the overlying conductors. The interface may be void-free.

[0030] In Figure 5A, a first dielectric layer 201 and multiple first conductors 202 are formed of a redistributed circuit structure. In some embodiments, the first dielectric layer 201 may be formed of a polymer material. For example, the polymer material of the first dielectric layer 201 may include multiple components such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO). The first dielectric layer 201 can provide a layer for the redistributed circuit structure 108 that can be formed on multiple die connectors 66, dielectric layers 68, and encapsulations 96, as described above with reference to Figure 4.

[0031] Taking the formation of multiple first conductive lines 202 as an example, a seed layer is formed on the first dielectric layer 201. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer of multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on top of the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). Then, a first mask structure 204 is formed on the seed layer and patterned. The first mask structure 204 can be formed by methods such as spin coating and can be patterned by exposure. The pattern of the first mask structure 204 corresponds to the multiple first conductive lines 202. This patterning forms multiple first openings 199 through the first mask structure 204 to expose the seed layer. Then, a conductive material is formed in the multiple first openings 199 of the first mask structure 204 and on the multiple exposed portions of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating). The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The combination of conductive material and multiple underlying portions of the seed layer forms multiple first conductive lines 202. The first mask structure 204 and multiple portions of the seed layer where no conductive material has formed are removed. The first mask structure 204 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the first mask structure 204 is removed, multiple exposed portions of the seed layer are also removed, for example using an acceptable etching process, such as wet etching or dry etching. The multiple remaining portions of the seed layer and the conductive material constitute the multiple first conductive lines 202.

[0032] In some embodiments, a plurality of first openings 199 in the first cover structure 204 have a geometry for providing a plurality of first conductors 202. In some embodiments, the plurality of first conductors 202 are configured to provide a horizontal electrical signal distribution across the package assembly 100.

[0033] The conductive filler material of the multilayer first conductor 202 can be plated to a thickness suitable for a low-resistance structure transmitting electrical signals. The entire height of the plurality of first openings 199 in the first mask structure 204 can be filled without plating the conductive filler material. In the embodiment shown in FIG. 5A, the upper surface of the conductive filler material is recessed relative to the upper surface of the first mask structure 204. In some embodiments, the first conductor 202 can have a height H1 ranging from 10 micrometers to 20 micrometers. In one example, the first conductor 202 has a height H1 of 15 micrometers.

[0034] In Figure 5B, a plurality of vias 203 are formed on top of a plurality of first conductors 202. The plurality of first vias 203 provide vertical electrical signal distribution through the encapsulation assembly 100. For example, the first vias 203 can transmit electrical signals from the underlying first conductors 202 to the underlying under-bump metallurgy (UBM) and / or second conductors.

[0035] Taking the formation of multiple vias 203 as an example, a second mask structure 205 can be formed on top of multiple first conductors 202, wherein multiple second openings 211 in the second mask structure 205 are filled with a second conductive material to provide multiple first vias 203. In some embodiments, the first mask structure 204 is removed before forming the second mask structure 205. When the first mask structure 204 is formed of photoresist material, it can be removed by wet chemical stripping and / or plasma ashing. After removing the first mask structure 204, the second mask structure 205 can be formed.

[0036] In some embodiments, the second mask structure 205 is formed of a photoresist material. The second mask structure 205 may be similar to the first mask structure 204. Therefore, the above description of the composition and method of forming the first mask structure 204 shown in FIG. 5A provides details of forming the second mask structure 205 shown in FIG. 5B. The thickness of the second mask structure deposition covers the entire plurality of first conductors 202, and its thickness at the top of the plurality of first conductors 202 is at least the height of the plurality of first vias 203.

[0037] In some embodiments, a photoresist layer of the second mask structure 205 is deposited and patterned using lithography to provide a plurality of second openings 211 having a geometry suitable for the plurality of first vias 203. As shown in FIG5B, the width of the plurality of second openings 211 is smaller than the width of the plurality of first openings 199. FIG5E shows a top view of a circular aperture of one embodiment of the geometry of the plurality of second openings 211. In some embodiments, the radius of the circular aperture providing the second openings 211 may be approximately 0.05 micrometers.

[0038] After forming the second cover structure 205, a plurality of second openings 211 can be filled with a conductive material to provide a plurality of first vias 203. In some embodiments, the conductive material formed within the plurality of second openings 211 to provide the plurality of first vias 203 can be a multilayer structure. In some embodiments, the conductive material of the plurality of first vias 203 may include at least one adhesive layer and a conductive filler. The adhesive layer and conductive filler of the first vias 203 are similar to the adhesive layer and conductive filler of the first wire 202.

[0039] In Figure 5C, the second masking structure 205 is removed, and a first dielectric layer 206 is formed on the first dielectric layer 201, the plurality of first conductive lines 202, and the plurality of first vias 203. In some embodiments, the first dielectric layer 206 is formed of a molding compound. The molding compound may include a resin in which fillers are disposed. Examples of resins include epoxy resins, acrylic or polyimide materials. Examples of fillers include silicon dioxide, etc. The molding compound may be applied by compression molding, transfer molding, or other methods, and may be applied in liquid or semi-liquid form, followed by curing. In some embodiments, the dielectric material of the first dielectric layer 206 may have a dielectric constant of less than 3.5.

[0040] The thickness of the first dielectric layer 206 is controlled to cover the upper surfaces of the plurality of first vias 203. For example, the first dielectric layer 206 may be deposited with a thickness having a height greater than the planarization plane P1. The planarization plane P1 is the height at which subsequent planarization steps terminate, so that the upper surface of the first dielectric layer 206 is planarized to be coplanar with the upper surfaces of the plurality of first vias 203.

[0041] In Figure 5D, the first dielectric layer 206 is planarized to expose the upper surfaces of the plurality of first vias 203. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) can be used to planarize the upper surfaces of the redistributed wiring structure 208. For example, the planarization process can continue until a planarization plane P1 is reached, as shown in Figure 5C. At the depth of the planarization plane P1, the upper surfaces of the first dielectric layer 206 are substantially coplanar with the upper surfaces of the plurality of first vias 203. For example, the height difference between any recesses on the upper surfaces of the first dielectric layer 206 and the upper surfaces of the plurality of first vias 203 is no greater than 0.25 micrometers. For example, the height difference between the upper surfaces of the first dielectric layer 206 and the upper surfaces of the plurality of first vias 203 may be in the range of 0.10 micrometers to 0.20 micrometers. In one example, the height difference between the upper surface of the first dielectric layer 206 and the upper surface of the first via 203 can be equal to 0.17 micrometers.

[0042] In Figure 5D, multiple second conductive lines 207 are formed on the planarized upper surface of the first dielectric layer 206 and the multiple first vias 203. The multiple second conductive lines 207 may be formed of a conductive material. In some embodiments, the multiple second conductive lines 207 may be formed of a seed layer 308 and a conductive material 309.

[0043] Taking the formation of multiple second conductive lines 207 as an example, a seed layer 308 is formed on the first dielectric layer 206 and multiple first vias 203. In some embodiments, the seed layer 308 is a metal layer, which can be a single layer or a composite layer of multiple sub-layers formed of different materials. In some embodiments, the seed layer 308 includes a titanium layer and a copper layer on top of the titanium layer. The seed layer 308 can be formed by, for example, physical vapor deposition (PVD). Then, a photoresist is formed on the seed layer 308 and patterned. The photoresist can be formed by spin coating or the like and can be exposed to be patterned. The pattern of the photoresist corresponds to the multiple second conductive lines 207. This patterning forms multiple openings through the photoresist to expose the seed layer 308. Then, a conductive material 309 is formed in the multiple openings of the photoresist and on the multiple exposed portions of the seed layer 308. The conductive material 309 can be formed by plating (e.g., electroplating or electroless plating). The conductive material 309 may include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material 309 and multiple underlying portions of the seed layer 308 forms multiple second conductive lines 207. The photoresist and multiple portions of the seed layer 308 where the conductive material 309 is not formed are removed. The photoresist can be removed through an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, multiple exposed portions of the seed layer 308 are removed, for example, by using an acceptable etching process, such as wet etching or dry etching. The multiple remaining portions of the seed layer 308 and the conductive material 309 constitute the multiple second conductive lines 207.

[0044] The redistribution structure 208 shown in Figure 4 comprises six layers of conductors and six layers of dielectric layers. It should be understood that any number of layers can be formed by repeating the steps described herein.

[0045] In FIG. 5F, a plurality of second vias 303 are formed, and a second dielectric layer 306 is formed. The plurality of second vias 303 may be similar to the plurality of first vias 203. Therefore, the description of forming the plurality of first vias 203 provided above with reference to FIG. 5A is suitable for describing the formation of the plurality of second vias 303 shown in FIG. 5F. The second dielectric layer 306 may be similar to the first dielectric layer 206 described above with reference to FIG. 5C. Therefore, the description of forming the first dielectric layer 206 provided above with reference to FIG. 5C is suitable for describing the formation of the second dielectric layer 306 shown in FIG. 5F.

[0046] Figure 5G is a perspective view of the interface 600 between a via (e.g., a first via 203 formed of copper) and a titanium adhesion layer (e.g., a seed layer 308 of the second conductor 207). The upper surface of the first via 203 is recessed compared to the upper surface of the first dielectric layer 206. The recess is small; in some embodiments, the depth difference between the upper surface of the first dielectric layer 206 and the upper surface of the first via 203 provided by the method described with reference to Figures 5A to 5F is no greater than 0.25 micrometers. As described above, by forming the first via 203, backfilling the first dielectric layer 206 to cover the first via 203, planarizing the backfilled first dielectric layer 206 and the upper surface of the first via 203, and then forming the second conductor 207 on top of the planarized first via 203 and the first dielectric layer 206, the difference between any recesses on the upper surface of the first dielectric layer 206 and the upper surface of the first via 203 can be minimized.

[0047] In Figure 5G, the difference between the upper surface of the first dielectric layer 206 and the upper surface of the first via 203 may be approximately 0.17 micrometers. In some embodiments, by minimizing the difference between the upper surface of the first dielectric layer 206 and the upper surface of the first via 203, the occurrence rate of voids at interface 600 is minimized or substantially eliminated. For example, the interface 600 between the adhesive layer of the overlying conductive feature (e.g., the second conductor 207) and the first via 203 is in direct contact with the planarized upper surface of the first dielectric layer 206, the planarized upper surface of the first via 203, and any sidewalls of the first filler material 206 caused by the depression between the planarized upper surface of the first filler material 206 and the planarized upper surface of the first via 203. The seed layer 308 extends along the upper surface of the first dielectric layer 206, extends downward along the sidewall of the first dielectric layer 206 forming the recess, and extends along the upper surface of the first via 203. There may be no gap between the seed layer 308 and the upper surface of the first dielectric layer 206, the sidewall of the first dielectric layer 206 forming the recess, or the upper surface of the first via 203.

[0048] In Figure 5G, there are no gaps between the lower surface of the second conductor 207 and any sidewalls of the first through-hole 203 and the first filler material 206. Therefore, there are no gaps between the second conductor 207 and the first through-hole 203. Furthermore, there are no gaps between the adhesive layer of the conductive material and the first through-hole 203.

[0049] In Figure 6, a plurality of under-bump metals 136 are formed to achieve external connections with the redistribution circuitry 108. The upper under-bump metals 136 have bump portions located on and extending along the upper surface of the upper dielectric layer 134 and the upper metallization pattern 132. As a result, the plurality of under-bump metals 136 are electrically coupled to a plurality of integrated circuit dies 50. The plurality of under-bump metals 136 can be formed in a manner similar to the multiple conductors of the redistribution circuitry 108 (as previously described), except that the plurality of under-bump metals 136 can have other types and numbers of layers. In some embodiments, the plurality of under-bump metals 136 have different dimensions than the metallization patterns 112, 116, 120, 124, 128, and 132.

[0050] In Figure 7, a substrate bonding separation technique is performed to separate the substrate 103 from the encapsulation 96 and the plurality of integrated circuit dies 50 (or "bonding separation"). In some embodiments, the bonding separation technique includes removing the substrate 103 and the adhesive layer 104 through a process such as polishing or planarization (e.g., CMP). After removal, the back surfaces of the plurality of integrated circuit dies 50 are exposed, and the back surfaces of the encapsulation 96 and the plurality of integrated circuit dies 50 are planarized. The structure is then placed on tape 138. As discussed further below, significant wafer warping occurs in the package assembly 100 when it bonds to the substrate 103.

[0051] In Figure 8, multiple conductive connectors 140 are formed on multiple bump under-metal 136. The multiple conductive connectors 140 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The multiple conductive connectors 140 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the multiple conductive connectors 140 are initially formed by forming a layer of solder or solder paste through methods such as vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once a layer of solder is formed on the structure, reflow soldering can be performed to shape the material into the desired bump shape.

[0052] In Figure 9, multiple sockets 142 and multiple connectors 143 are attached to the redistribution structure 108. The sockets 142 and multiple connectors 143 are interfaces for external connection to the encapsulation assembly 100. The sockets 142 and multiple connectors 143 include multiple pads 144, such as aluminum pads, for external connection. The sockets 142 and multiple connectors 143 are mounted to multiple under-bump metal 136 using multiple conductive connectors 140. In the illustrated embodiment, the sockets 142 are attached to computing stations 101A and 101B, while the connectors 143 are attached to connection station 102A. An underfill 146 is formed to fill the gaps between the sockets 142 and multiple connectors 143 and the redistribution structure 108. The underfill 146 can be formed by a capillary flow process after the multiple sockets 142 and multiple connectors 143 are attached, or it can be formed by a suitable deposition method before the multiple sockets 142 and multiple connectors 143 are attached.

[0053] Multiple sockets 142 serve as the electrical and physical interfaces for multiple modules (discussed further below) that can be installed at computing stations 101A and 101B after the package assembly 100 is manufactured. For example, a user of the package assembly 100 can install multiple modules in the multiple sockets 142 to form a complete functional system at computing stations 101A and 101B. The type of module selected for installation depends on the type of functional system required at computing stations 101A and 101B. Examples of modules that can be installed in the multiple sockets 142 include memory modules, voltage regulator modules, power supply modules, integrated passive device (IPD) modules, etc. The multiple sockets 142 may include different components, such as chassis and contact pins, which may be composed of different materials.

[0054] Multiple connectors 143 serve as electrical and physical interfaces between the packaged assembly 100 and external systems. For example, when the packaged assembly 100 is mounted as part of a larger external system (such as a data center), multiple connectors 143 can be used to couple the packaged assembly 100 to the external system. Examples of multiple connectors 143 include receivers for ribbon cables, flexible printed circuits, etc.

[0055] Multiple sockets 142 and multiple connectors 143 can be attached to the redistribution structure 108 in various layouts. The layout shown in Figure 9 is one example. Figure 10 is a top view of the package assembly 100, showing another exemplary layout of the multiple sockets 142 and multiple connectors 143. Each socket 142 is directly located above and electrically coupled to the SoC die 50A of the corresponding computing station 101A or computing station 101B. Multiple connectors 143 are arranged around the periphery of the package assembly 100, thereby increasing the usable area of ​​the multiple sockets 142. Connection portion 102A may include one or more connectors 143. In the illustrated embodiment, the multiple connectors 143 are laterally offset from the multiple I / O interface dies 50B. In another embodiment, the multiple connectors 143 are directly located above the multiple I / O interface dies 50B.

[0056] In Figure 11, multiple bolt holes 148 are formed through the encapsulation assembly 100. The multiple bolt holes 148 can be formed by drilling processes such as laser drilling or mechanical drilling. The multiple bolt holes 148 can be formed by drilling a contour for the multiple bolt holes 148 using a drilling process, and then removing the material separating the contours.

[0057] Figures 12 and 13 show various views of the process of securing the package assembly 100 between the thermal module 200 and the mechanical support 300 according to some embodiments. The thermal module 200 may be a heat sink, heat spreader, cold plate, etc. The mechanical support 300 is a rigid support that partially physically engages with a plurality of sockets 142, securing the sockets 142 during module installation or removal. Clamping the package assembly 100 between the thermal module 200 and the mechanical support 300 reduces warpage of the package assembly 100 (e.g., warpage caused by separation of the carrier substrate). Figure 12 is a quarter-size three-dimensional view of the package assembly 100, thermal module 200, and mechanical support 300 during assembly according to some embodiments. For clarity, some details are omitted in Figure 12. Figure 13 is a cross-sectional view showing portions of the assembled package assembly 100, thermal module 200, and mechanical support 300, and is described in conjunction with Figure 12. Figure 13 is shown along reference section BB of Figure 12.

[0058] The encapsulation assembly 100 is removed from tape 138 and secured between the thermal module 200 and the mechanical support 300 using a plurality of bolts 1202. The bolts 1202 pass through a plurality of bolt holes 148 in the encapsulation assembly 100, through corresponding bolt holes 1204 in the thermal module 200, and through corresponding bolt holes 1302 in the mechanical support 300. A plurality of fasteners 1206 are screwed into and tightened onto the bolts 1202 to clamp the encapsulation assembly 100 between the thermal module 200 and the mechanical support 300. For example, the fasteners 1206 may be nuts screwed onto the bolts 1202. The fasteners 1206 are attached to both sides of the resulting system-on-wafer assembly (e.g., on the side with the thermal module 200 (sometimes referred to as the back side) and on the side with the mechanical support 300 (sometimes referred to as the front side)).

[0059] Before fastening the individual components together, a thermal interface material (TIM) 1208 (see Figure 13) is applied to the back side of the package assembly 100 to physically and thermally couple the thermal module 200 to the plurality of integrated circuit dies 50. During fastening, a plurality of fasteners 1206 are tightened, thereby increasing the mechanical force exerted on the package assembly 100 by the thermal module 200 and the mechanical support 300. The plurality of fasteners 1206 are tightened until the thermal module 200 applies the required pressure to the TIM 1208.

[0060] Figure 14 shows a cross-sectional view of the system-on-wafer assembly obtained after mounting multiple modules 400 into multiple sockets 142. Figure 14 is shown along reference section BB of Figure 12. As described above, the multiple modules 400 may be memory modules, voltage regulator modules, power supply modules, integrated passive device (IPD) modules, etc. The multiple modules 400 include multiple conductive connectors 402 that are inserted into corresponding receivers to physically and electrically couple the contacts of the multiple sockets 142. In this way, the multiple modules 400 are fixed in the multiple sockets 142, forming a complete functional system at computing stations 101A and 101B. After installation, the multiple modules 400 are located within multiple openings 1304 of the mechanical support 300.

[0061] In some embodiments, this method and structure can provide a redistribution circuit fabrication process that offers excellent alignment conditions and a high-quality interface between the upper surface of the via and the overlay conductor. In some embodiments, the recess between the upper surface of the via and the upper surface of the surrounding dielectric layer is limited to a height difference of 0.5 micrometers or less between the upper surface of the dielectric layer and the via surface. By reducing the recess on the upper surface of the via, the adhesion layer coverage (e.g., titanium coverage) of the overlay conductor can be up to 100%. In some embodiments, the occurrence rate of voids at the interface between the via and the conductor is substantially eliminated.

[0062] According to one embodiment, the method includes: forming a first conductive material in a first opening of a first mask structure to provide a first conductor; forming a second conductive material in a second opening of a second mask structure to provide a via on the first conductor; removing the second mask structure; forming a dielectric layer covering the first conductor and the via; planarizing the dielectric layer to expose an upper surface of the via, wherein the upper surface of the via is recessed relative to the upper surface of the dielectric layer after planarization; and forming a conductive feature including a seed layer on top of the upper surface of the via, wherein the seed layer covers the upper surface of the via and the upper surface of the dielectric layer. In one embodiment, the method further includes removing the first mask structure before forming the second mask structure. In some embodiments, the seed layer covers the sidewalls of the dielectric layer between the upper surface of the via and the upper surface of the dielectric layer. In some embodiments, the height difference between the upper surface of the via and the upper surface of the dielectric layer after planarization of the dielectric layer is less than 0.15 micrometers. In one embodiment, the conductive feature includes a second conductive line. In one embodiment, the conductive feature includes under-bump metal. In one embodiment, the seed layer includes titanium and copper on titanium. In one embodiment, the seed layer completely covers the via from one edge of the upper surface of the via to the opposite second edge of the upper surface of the via, and there are no gaps between the seed layer and the upper surface of the via.

[0063] According to another embodiment, the method includes forming a redistribution wiring structure, including forming a first via in a first opening of a first mask structure, removing the first mask structure, forming a first dielectric layer covering the first via, planarizing the first dielectric layer to expose an upper surface of the first via, and forming a bump under-metal with a first seed layer on top of the upper surface of the first via, wherein the first seed layer of the bump under-metal completely covers a first interface between the bump under-metal and the first via. The method may further include attaching a module socket to the bump under-metal of the redistribution wiring structure. In one embodiment, after planarizing the first dielectric layer, the height difference between the upper surface of the first via and the upper surface of the first dielectric layer is less than 0.15 micrometers. In one embodiment, the first seed layer comprises titanium and copper on titanium. In one embodiment, the method further includes forming a conductor on a second via, wherein the first via is formed on the conductor. In one embodiment, forming the conductor includes forming a conductive material in a second opening of the second mask structure to provide the conductor, wherein the second opening exposes the planarized upper surface of the second via and removes the second mask structure.

[0064] According to another embodiment, the device includes a redistribution wiring structure including a via extending through a dielectric layer to a first conductor, wherein the upper surface of the via is recessed relative to the upper surface of the dielectric layer, and wherein the height difference between the upper surface of the via and the upper surface of the dielectric layer is no greater than 0.15 micrometers; and an under-bump metal including a seed layer located on top of the upper surface of the via and the upper surface of the dielectric layer, wherein the seed layer completely covers the interface between the under-bump metal and the upper surface of the via, the interface having no gaps; and a module socket connected to the under-bump metal. In some embodiments, the device further includes a thermal module; and a mechanical support, the redistribution wiring structure disposed between the thermal module and the mechanical support. In some embodiments, the device further includes a plurality of bolts extending through the mechanical support, the thermal module, and the redistribution wiring structure. In some embodiments, the seed layer includes titanium and copper. In some embodiments, the device further includes a voltage regulator module located in the module socket. In some embodiments, the seed layer has a conformal thickness and includes a sidewall portion on a portion of the dielectric layer located between the upper surface of the via and the upper surface of the dielectric layer. In some embodiments, the seed layer completely and continuously covers the via from one edge of the upper surface of the via to an opposite second edge of the upper surface of the via.

[0065] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the scope of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0066] 50: Integrated circuit die 50A: SoC die 50B: I / O interface grain 52: Semiconductor substrate 62: Connecting pad 64: Passivation film 66: Grain connector 68: Dielectric layer 96: Encapsulation 100: Encapsulated Components 101, 101A, 101B: Computing stations 102, 102A: Connecting stations 103: Supporting base 104: Adhesive layer 108: Re-layout circuit structure 110, 114, 118, 122, 126, 130, 134: Dielectric layers 112, 116, 120, 124, 128, 132: Metallized patterns 136: Under-bump metal 138: Tape 140: Conductive connector 142: Socket 143: Connector 144: Connector 146: Bottom filler 148, 1204, 1302: Bolt holes 199: First Opening 200: Thermal Module 201: First dielectric layer 202: First conductor 203: Through-hole / First Through-hole 204: First curtain structure 205: Second curtain structure 206: First dielectric layer / first filler material 207: Second conductor 211: Second opening 300: Mechanical support 303: Second via 306: Second dielectric layer 308: Seed layer 309: Conductive Materials 400: Module 402: Conductive connector 600: Interface 1202: Bolt 1208: Thermal interface materials 1304: Opening H1: Height P1: Flattened plane

Claims

1. A method for manufacturing a semiconductor device, comprising: A first conductive material is formed in the first opening of the first curtain structure to provide a first conductor; A second conductive material is formed in a second opening of a second masking structure to provide a via on the first conductor; the second masking structure is removed; a dielectric layer is formed covering the first conductor and the via; the dielectric layer is planarized to expose the upper surface of the via, wherein the upper surface of the via is recessed relative to the upper surface of the dielectric layer after planarization; and a conductive feature including a seed layer is formed on top of the upper surface of the via, wherein the seed layer covers the upper surface of the via and the upper surface of the dielectric layer.

2. The method of manufacturing a semiconductor device as claimed in claim 1 further includes removing the first mask structure before forming the second mask structure.

3. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the seed layer covers the sidewall of the dielectric layer between the upper surface of the via and the upper surface of the dielectric layer.

4. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the height difference between the upper surface of the via and the upper surface of the dielectric layer after the planarization of the dielectric layer is less than 0.15 micrometers.

5. A method for manufacturing a semiconductor device, comprising: Forming a redistribution wiring structure includes: forming a first via in a first opening of a first mask structure; removing the first mask structure; forming a first dielectric layer covering the first via; planarizing the first dielectric layer to expose an upper surface of the first via; and forming a bump under-metal, including a first seed layer on top of the upper surface of the first via, wherein the first seed layer of the bump under-metal completely covers a first interface between the bump under-metal and the first via; and attaching a module socket to the bump under-metal of the redistribution wiring structure.

6. A method of manufacturing a semiconductor device as claimed in claim 5, wherein the height difference between the upper surface of the first via and the upper surface of the first dielectric layer after the planarization of the first dielectric layer is less than 0.15 micrometers.

7. A semiconductor device, comprising: The redistributed wiring structure includes: a via extending through a dielectric layer to a first conductor, wherein the upper surface of the via is recessed relative to the upper surface of the dielectric layer, and wherein the height difference between the upper surface of the via and the upper surface of the dielectric layer is no greater than 0.15 micrometers; and under-bump metal, including a seed layer located on top of the upper surface of the via and the upper surface of the dielectric layer, wherein the seed layer completely covers the interface between the under-bump metal and the upper surface of the via, the interface having no gaps; and a module socket connected to the under-bump metal.

8. The semiconductor device as claimed in claim 7, further comprising: Thermal module; And a mechanical support, wherein the redistribution circuit structure is disposed between the thermal module and the mechanical support.

9. The semiconductor device of claim 7, wherein the seed layer has a conformal thickness and includes a sidewall portion on a portion of the dielectric layer located between the upper surface of the via and the upper surface of the dielectric layer.

10. The semiconductor device of claim 7, wherein the seed layer completely and continuously covers the via from one edge of the upper surface of the via to the opposite second edge of the upper surface of the via.

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