Interconnect stack and a method for forming the same

Abstract

This application provides a method for forming an interconnect stack, the method comprising: providing a first semiconductor wafer having a plurality of first semiconductor cells, each first semiconductor cell having a set of first conductive interconnect structures extending through the first semiconductor wafer; providing a second semiconductor wafer having a plurality of second semiconductor cells, each second semiconductor cell having a set of second conductive interconnect structures extending through the second semiconductor cell; dicing the second semiconductor wafer into a plurality of second semiconductor dies; vertically aligning each second semiconductor die with a first semiconductor cell; bonding each second semiconductor die to a first semiconductor cell by hybrid bonding; dicing the first semiconductor wafer into a plurality of first semiconductor dies to form a plurality of double-layer interconnect sub-stacks; testing each double-layer interconnect sub-stack to select a plurality of qualified double-layer interconnect sub-stacks; and bonding two qualified double-layer interconnect sub-stacks to form an interconnect stack.

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