Substrate having stack via and method of manufacturing the same
TW202635141APending Publication Date: 2026-08-16CHIPBOND TECH
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Patent Information
- Application Number
- TW115117899
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-08-16
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Abstract
A substrate having stack via includes a first dielectric layer, a first conductive layer, a first conductive material, a second dielectric layer, a second conductive layer and a second conductive material. The first conductive layer and the first conductive material formed in the first dielectric layer, and the second conductive layer and the second conductive material formed in the second dielectric layer are formed of a stack via. Dielectric material used to form the first and second dielectric layers will not remain in the stack via during manufacturing. Thus, the second conductive layer can be electrically connected to the first conductive material, the contact area between the first conductive layer and the first conductive material and the contact area between the second conductive layer and the second conductive material can satisfy specification requirements for electrical transmission.
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