Stacked structure and design method of its bonding layer

Abstract

A stacked structure and a design method of its bonding layer are provided. The design method includes the following steps. A first stacked structure formed by stacking and bonding of multiple wafers is provided. The first stacked structure includes die regions, bonding test regions and scribe lines. The scribe lines separate the die regions, and the bonding test regions are located in the scribe lines. Each bonding test region includes a test circuit. The test circuit includes conductive bonding structures formed by bond pads of wafers bonding to each other. The bond pads in each of the bonding test regions have different design parameters. Electrical performance test is performed on the test circuit of each of the bonding test regions of the first stacked structure. A range of applicable design parameters of bond pads in the die regions of the first stacked structure is determined by a test result of the electrical performance test.

Description

[Technical Field]

[0001] This invention relates to a structure and a design method thereof, and more particularly to a design method for a stacked structure and its bonding layer. [Previous Technology]

[0002] Generally, to achieve efficient computing, multiple wafers are stacked to form a stacked structure. In the front-end process, automated tools can be used to determine or verify the process window. However, in the back-end bonding process, these automated tools cannot be used, making it difficult to predict relevant bonding parameters, such as bonding pad design parameters, bonding process parameters, and the number of wafers stacked. If bonding fails during the design testing process, the entire stacked structure is lost, and corresponding design modifications to the die area layout are required, leading to increased design costs and low execution efficiency. Therefore, improving the design of the bonding layer in the stacked structure is a current goal that needs to be addressed. [Summary of the Invention]

[0003] The present invention provides a design method for a stacked structure and its bonding layer, which can effectively reduce design costs and improve efficiency.

[0004] The design method of the bonding layer of the stacked structure of the present invention includes the following steps. A first stacked structure is provided, which is formed by stacking and bonding multiple wafers. The first stacked structure has multiple grain regions, multiple bonding test regions, and dicing channels. The dicing channels separate the multiple grain regions, and the multiple bonding test regions are located in the dicing channels. Each of the multiple bonding test regions of the first stacked structure includes a test line. The test line of the first stacked structure includes a conductive bonding structure formed by bonding pads of multiple wafers bonding with each other. The bonding pads of each of the multiple wafers in the multiple bonding test regions of the first stacked structure have different design parameters. Electrical measurements are performed on the test lines of the multiple bonding test regions of the first stacked structure. The range of available design parameters for the bonding pads in the multiple grain regions of the first stacked structure is determined based on the results of the electrical measurements.

[0005] The stacked structure of the present invention includes a first wafer and a second wafer. The first wafer includes a plurality of first die regions, a first dicing channel, and a plurality of first bonding test regions. The first dicing channel separates the plurality of first die regions. The plurality of first bonding test regions are located in the first dicing channel, wherein the plurality of first bonding test regions include a first region and a second region, the first region including a plurality of first bonding pads, and the second region including a plurality of second bonding pads. The second wafer includes a plurality of second die regions, a second dicing channel, and a plurality of second bonding test regions. The second dicing channel separates the plurality of second die regions. The plurality of second bonding test regions are located in the second dicing channel, wherein the plurality of second bonding test regions include a third region and a fourth region, the third region including a plurality of third bonding pads, and the fourth region including a plurality of fourth bonding pads. The bonding pads in the plurality of second die regions of the second wafer are in direct contact with the corresponding bonding pads in the plurality of first die regions of the first wafer, the plurality of third bonding pads in the third region of the second wafer are in direct contact with the plurality of first bonding pads in the first region of the first wafer, and the plurality of fourth bonding pads in the fourth region of the second wafer are in direct contact with the plurality of second bonding pads in the second region of the first wafer.

[0006] Based on the above, the stacked structure of the present invention, by setting multiple bonding test areas in the dicing channel, can perform electrical measurements on the test circuits of multiple bonding test areas to determine the feasible range of design parameters of bonding pads, bonding process parameters and number of wafers stacked in the stacked structure, and adjust the design of bonding layers in the stacked structure based on the obtained feasible ranges without affecting the layout design of the die region in the stacked structure. This can effectively reduce design costs and provide a design basis for further miniaturization or changes of the future stacked structure.

Implementation Method

[0007] Please refer to Figures 1 to 5, wherein Figure 2 only schematically illustrates the bonding layer 110 of the first wafer W1 and the bonding layer 210 of the second wafer W2, and marks the positions of the die region DR, dicing track SL and bonding test region TR, while omitting the drawing of other components. The design method S10 of the bonding layer of the stacked structure includes the following steps. First, in block S100, a first stacked structure 10 is provided. The first stacked structure 10 is formed by stacking and bonding multiple wafers (e.g., the first wafer W1 and the second wafer W2). In some embodiments, as shown in Figures 2 to 4, the first wafer W1 includes a substrate 100, a bonding layer 110 and an interconnect structure 120, the bonding layer 110 is disposed on the substrate 100, and the interconnect structure 120 is disposed between the substrate 100 and the bonding layer 110. Similarly, the second wafer W2 includes a substrate 200, a bonding layer 210, and an interconnect structure 220. The bonding layer 210 is disposed on the substrate 200, and the interconnect structure 220 is disposed between the substrate 200 and the bonding layer 210. The bonding layer 110 of the first wafer W1 and the bonding layer 210 of the second wafer are disposed face-to-face, and a first stacked structure 10 is formed by hybrid bonding. In some embodiments, the first wafer W1 may be a base wafer, an interposer, or a memory wafer, and the second wafer W2 may be a memory wafer.

[0008] In some embodiments, substrates 100 and 200 may include semiconductor materials such as silicon, germanium, silicon carbide, gallium arsenide, gallium nitride, or other suitable materials. In some embodiments, devices (not shown), such as active elements, passive elements, or other suitable devices, may be disposed in or on substrates 100 and 200. The interconnect structure 120 may include a plurality of staggered conductive layers 122 and dielectric layers 124 to provide internal circuitry for the first wafer W1; the interconnect structure 220 may include a plurality of staggered conductive layers 222 and dielectric layers 224 to provide internal circuitry for the second wafer W2.

[0009] In some embodiments, the bonding layer 110 may include a plurality of bonding pads 112, a plurality of bonding vias 114, and a bonding dielectric layer 116. The plurality of bonding pads 112 and the plurality of bonding vias 114 are disposed in the bonding dielectric layer 116. The bonding vias 114 are disposed between the bonding pads 112 and the interconnect structure 120 to electrically connect the bonding pads 112 and the conductive layer 122 of the interconnect structure 120. Alternatively, the bonding layer 210 may include a plurality of bonding pads 212, a plurality of bonding vias 214, and a bonding dielectric layer 216. The plurality of bonding pads 212 and the plurality of bonding vias 214 are disposed in the bonding dielectric layer 216. The bonding vias 214 are disposed between the bonding pads 212 and the interconnect structure 220 to electrically connect the bonding pads 212 and the conductive layer 222 of the interconnect structure 220.

[0010] In some embodiments, a plurality of bonding pads 112 of the first wafer W1 can be metal-to-metal bonded to a plurality of bonding pads 212 corresponding to the second wafer W2, and a bonding dielectric layer 116 of the first wafer W1 can be dielectric-to-dielectric bonded to the bonding dielectric layer 216 of the second wafer W2, thereby forming a bonding structure between the interfaces of the first wafer W1 and the second wafer W2. Through the bonding pads 112 and 212, the first wafer W1 and the second wafer W2 can be electrically connected to each other to form a first stacked structure 10. In this embodiment, the bonding process of the first wafer W1 and the second wafer W2 is performed under preset process conditions.

[0011] In some embodiments, the materials of conductive layer 122 and conductive layer 222, bonding pad 112 and bonding pad 212, and bonding via 114 and bonding via 214 may include copper, aluminum, gold, tungsten, silver, platinum, titanium, tantalum, alloys thereof, or other suitable conductive materials. In some embodiments, the materials of dielectric layer 124 and dielectric layer 224, and bonding dielectric layer 116 and bonding dielectric layer 216 may include silicon oxide, polyimide, or other suitable dielectric materials.

[0012] In some embodiments, as shown in FIG4, the first wafer W1 may include a plurality of first grain regions DR1, a plurality of bonding test regions TR1, and a first dicing track SL1. The plurality of first grain regions DR1 are arranged in an array with respect to each other, and the first dicing track SL1 separates the plurality of first grain regions DR1. The first dicing track SL1 may include a plurality of dicing tracks extending along the x direction and arranged in the y direction, and a plurality of dicing tracks extending along the y direction and arranged in the x direction. The plurality of bonding test regions TR1 are located in the first dicing track SL1 to provide bonding pads 112 with different design parameters for subsequent bonding tests. For example, the plurality of bonding test regions TR1 may include bonding test regions TR1a, TR1b, TR1c, TR1d, TR1e, and TR1f. In some embodiments, bonding test regions TR1a, TR1b, and TR1c are arranged in one first dicing track SL1 extending along the x direction, and bonding test regions TR1d, TR1e, and TR1f are arranged in another first dicing track SL1 extending along the x direction. However, the present invention is not limited thereto. The bonding test areas TR1a, TR1b, TR1c, TR1d, TR1e and TR1f can be set in any of the first cutting channels SL1, and the number of bonding test areas can be adjusted according to actual needs.

[0013] In some embodiments, the plurality of bonding pads 112 may be located in the plurality of first grain regions DR1 and the plurality of bonding test regions TR1. For ease of distinction, the bonding pads 112 located in the plurality of first grain regions DR1 are referred to as bonding pads 112a, and the bonding pads 112 located in the plurality of bonding test regions TR1 are referred to as bonding pads 112b.

[0014] The bonding pads 112a located in the plurality of first grain regions DR1 have design parameters preset in the initial design stage, while the bonding pads 112b located in the plurality of bonding test regions TR1 each include different design parameters, wherein the design parameters of the bonding pads may include parameters such as the shape, size, and spacing of the bonding pads. For example, the bonding pads 112b in bonding test regions TR1a, TR1b and TR1c are all circular in shape, but the size (e.g., diameter) and / or spacing of the bonding pads 112 in bonding test region TR1a is smaller than the size (e.g., diameter) and / or spacing of the bonding pads 112 in bonding test region TR1b, and the size (e.g., diameter) and / or spacing of the bonding pads 112 in bonding test region TR1b is smaller than the size (e.g., diameter) and / or spacing of the bonding pads 112 in bonding test region TR1c. On the other hand, the mating pads 112b in the mating test areas TR1d, TR1e, and TR1f are all squares with rounded corners. However, the dimensions (e.g., length and / or width) and / or spacing of the mating pads 112b in mating test area TR1d are smaller than those in mating test area TR1e, and the dimensions (e.g., length and / or width) and / or spacing of the mating pads 112b in mating test area TR1e are smaller than those in mating test area TR1f. In this way, mating pads 112b with different design parameters can be respectively arranged in different mating test areas TR1.

[0015] The bonding pads in Figures 6A to 6C can be bonding pads of the first wafer W1 or the second wafer W2. In some embodiments, the shape (in top view) of the bonding pad 112b of the bonding test area TR1 can be circular (as shown in Figure 6A), elliptical, square (as shown in Figure 6B), rectangular, square with rounded corners (as shown in Figure 6C), rectangle with rounded corners, triangle, hexagon, octagon, or other shapes. In some embodiments, the dimension d1 of the bonding pad 112b of the bonding test area TR1 (e.g., the width measured in the x-direction or the length measured in the y-direction or the diameter of a circle) can be between 0.5 μm and 5 μm. In some embodiments, the spacing d2 of the bonding pads 112b of the bonding test area TR1 refers to the distance between the centers of two adjacent bonding pads 112, and the spacing d2 can be between 2 μm and 15 μm. In some embodiments, the ratio of the size d1 of the bonding pad 112b to the distance d3 between the bonding dielectric layer 116 between two adjacent bonding pads 112b (i.e., d1 / d3) < 0.4 may help improve the bonding strength.

[0016] Similarly, as shown in FIG5, the second wafer W2 may include a plurality of second grain regions DR2, a plurality of bonding test regions TR2, and a second dicing track SL2, which correspond to the first grain region DR1, the plurality of bonding test regions TR1, and the first dicing track SL1 of the first wafer W1, respectively. The plurality of second grain regions DR2 are arranged in an array with each other, and the second dicing track SL2 separates the plurality of second grain regions DR2. The second dicing track SL2 may include a plurality of dicing tracks extending along the x-direction and arranged in the y-direction, and a plurality of dicing tracks extending along the y-direction and arranged in the x-direction. The plurality of bonding test regions TR2 are located in the second dicing track SL2 to provide bonding pads 212 with different design parameters for subsequent bonding tests. For example, the plurality of bonding test regions TR2 may include bonding test regions TR2a, TR2b, TR2c, TR2d, TR2e, and TR2f, which correspond to the bonding test regions TR1a, TR1b, TR1c, TR1d, TR1e, and TR1f of the first wafer W1, respectively. In some embodiments, the bonding test areas TR2a, TR2b, and TR2c are arranged in a second cutting channel SL2 extending along the x-direction, and the bonding test areas TR2d, TR2e, and TR2f are arranged in another second cutting channel SL2 extending along the x-direction. However, the present invention is not limited thereto; the bonding test areas TR2a, TR2b, TR2c, TR2d, TR2e, and TR2f can be arranged in any second cutting channel SL2, and the number of bonding test areas TR2 can be adjusted according to actual needs, provided that the positions and numbers of the multiple bonding test areas TR2 correspond to the positions and numbers of the multiple bonding test areas TR1.

[0017] In some embodiments, a plurality of bonding pads 212 may be located in a plurality of second grain regions DR2 and a plurality of bonding test regions TR2. For ease of distinction, the bonding pads 212 located in the plurality of second grain regions DR2 are referred to as bonding pads 212a, and the bonding pads 212 located in the plurality of bonding test regions TR2 are referred to as bonding pads 212b.

[0018] The bonding pads 212a located in the plurality of second grain regions DR2 have design parameters preset in the initial design stage, while the bonding pads 212b located in the plurality of bonding test regions TR2 each include different design parameters and correspond to the bonding pads 112b in the plurality of bonding test regions TR1 to facilitate bonding with the bonding pads 112b in the plurality of bonding test regions TR1. For example, the shape, size, and spacing of the bonding pads 212b in the bonding test areas TR2a, TR2b, and TR2c are substantially the same as the shape, size, and spacing of the bonding pads 112b in the corresponding bonding test areas TR1a, TR1b, and TR1c. Therefore, the shape of the bonding pads 212b in the bonding test areas TR2a, TR2b, and TR2c is circular. The size (e.g., diameter) and / or spacing of the bonding pads 212b in the bonding test area TR2a is smaller than the size (e.g., diameter) and / or spacing of the bonding pads 212b in the bonding test area TR2b, and the size (e.g., diameter) and / or spacing of the bonding pads 212b in the bonding test area TR2b is smaller than the size (e.g., diameter) and / or spacing of the bonding pads 212b in the bonding test area TR2c. On the other hand, the shape, size, and spacing of the mating pads 212b in the mating test areas TR2d, TR2e, and TR2f are essentially the same as those in the corresponding mating test areas TR1d, TR1e, and TR1f. Therefore, the mating pads 212b in the mating test areas TR2d, TR2e, and TR2f are all squares with rounded corners. The dimensions (e.g., length and / or width) and / or spacing of the mating pads 212b in the mating test area TR2d are smaller than the dimensions (e.g., diameter) and / or spacing of the mating pads 212b in the mating test area TR2e, and the dimensions (e.g., length and / or width) and / or spacing of the mating pads 212b in the mating test area TR2e are smaller than the dimensions (e.g., diameter) and / or spacing of the mating pads 212b in the mating test area TR2f. In this way, mating pads 212b with different design parameters can be respectively set in different mating test areas TR2.

[0019] In some embodiments, a plurality of second grain regions DR2 of the second wafer W2 correspond to a plurality of first grain regions DR1 of the first wafer W1, and the bonding pads 212a of the plurality of second grain regions DR2 are bonded to the bonding pads 112a of the plurality of first grain regions DR1 to form a plurality of grain regions DR of the first stacked structure 10. A second dicing sl2 of the second wafer W2 corresponds to a first dicing sl1 of the first wafer W1, and together they form a dicing sl of the first stacked structure 10. A plurality of bonding test regions TR2 of the second wafer W2 correspond to a plurality of bonding test regions TR1 of the first wafer W1, and the bonding pads 212b of the plurality of bonding test regions TR2 are bonded to the bonding pads 112b of the plurality of bonding test regions TR1 to form a plurality of bonding test regions TR of the first stacked structure 10. That is, the first stacked structure 10 includes a plurality of grain regions DR, a plurality of bonding test regions TR, and dicing sl. The plurality of grain regions DR are arranged in an array with each other and separated by dicing sl, and the plurality of bonding test regions TR are located in the dicing sl.

[0020] In some embodiments, each of the plurality of bonding test areas TR of the first stack structure 10 includes a test line C1 (shown as dashed lines in FIG. 3, where arrows indicate external connections for power measurement), the test line C1 traveling between the first wafer W1 and the second wafer W2. In some embodiments, the test line C1 is a daisy chain line, with half of the line in the first wafer W1 and the other half in the second wafer W2. Therefore, the test line C1 includes a plurality of conductive bonding structures formed by bonding pads 112b of the first wafer W1 located in bonding test area TR1 and bonding pads 212b of the second wafer W2 located in bonding test area TR2 bonded to each other. The plurality of conductive bonding structures can be interconnected with each other via bonding vias 114 and conductive layer 122 and conductive layer 222 of bonding vias 214 to form the test line C1.

[0021] Please refer to Figure 1. In block S110, electrical measurements, such as resistance measurement or other electrical measurements, are performed on the test lines C1 of the multiple junction test areas TR of the first stack structure 10.

[0022] Referring to Figure 1, in block S120, the available design parameter range of the bonding pads 112 and 212 of the first stacked structure 10 is determined by the results of electrical measurements. In some embodiments, the measured resistance values ​​and the corresponding design parameters of the bonding pads 112b and 212b can be plotted to determine the available design parameter range of the bonding pads 112b and 212b. For example, as shown in Figure 7, a relationship diagram between the spacing and shape of the bonding pads and the resistance value can be plotted. As shown in Figure 7, when the bonding pads 112b and 212b are square, when the spacing of the bonding pads 112b and 212b is less than about 5 μm, the resistance value of the test line C1 is greater than the target range; when the spacing of the bonding pads 112b and 212b is more than about 5 μm, the resistance value of the test line C1 falls within the target range. It can be seen that when the bonding pads 112b and 212b are square, the available spacing range of the bonding pads 112b and 212b is more than about 5 μm. When bonding pads 112b and 212b are squares with rounded corners, and the spacing between bonding pads 112b and 212b is less than about 6 μm, the resistance value of test circuit C1 is greater than the target range; when the spacing between bonding pads 112b and 212b is greater than about 6 μm, the resistance value of test circuit C1 falls within the target range. It can be seen that when bonding pads 112b and 212b are squares with rounded corners, the usable spacing range of bonding pads 112b and 212b is greater than about 6 μm. When the bonding pads 112b and 212b are circular, and the spacing between them is less than approximately 10 μm, the resistance value of the test circuit C1 is greater than the target range. When the spacing between the bonding pads 112b and 212b is greater than approximately 10 μm, the resistance value of the test circuit C1 falls within the target range. Therefore, when the bonding pads 112b and 212b are circular, the usable spacing range of the bonding pads 112b and 212b is greater than approximately 10 μm. The above example is intended to clearly illustrate how to determine the usable spacing range of the bonding pads 112b and 212b using the results of electrical measurements, and is not intended to limit the present invention. It should be understood that the numerical range of the spacing mentioned above is only for illustrative purposes and is not intended to limit the present invention. Here, the target range of the resistance value can be ±5% to ±10% of the target value Ro, and the target value Ro can be set according to different applications, but the present invention is not limited thereto. The target range of the resistance value can also be defined as upper and lower limits according to the established specifications (spec). Similarly, a graph showing the relationship between the size and shape of the bonding pads and their resistance values ​​can be drawn to obtain the available size range of bonding pads 112b and 212b with different shapes.

[0023] In some embodiments, by using the available design parameter range of the bonding pads 112b and 212b obtained above, it can be determined whether the design parameters of the bonding pads 112a and 212a in the first stacked structure 10 located in the grain region DR are within the available design parameter range. If the design parameters of the bonding pads 112a and 212a in the grain region DR are within the available design parameter range, it indicates that the design parameters of the bonding pads 112a and 212a in the grain region DR are feasible. If the design parameters of the bonding pads 112a and 212a in the grain region DR are outside the available design parameter range, the design parameters of the bonding pads 112a and 212a in the grain region DR can be modified according to the obtained available design parameter range of the bonding pads 112b and 212b. Since the bonding test area of ​​the first stacked structure 10 is located in the dicing channel SL rather than in the die region DR, the photomask design of the bonding layer 110 of the first wafer W1 and the bonding layer 120 of the second wafer W2 only needs to be modified according to the aforementioned range of available design parameters, without affecting the internal design of the die region DR, thus reducing the overall design cost.

[0024] In some embodiments, based on current process conditions and industry requirements (e.g., number of input / output (I / O) ports, cost considerations, space considerations, process capability, etc.), the optimal combination of design parameters for the bonding pads 112a and 212a of the die region DR of the first stacked structure 10 can be obtained through the available design parameter range of the bonding pads 112b and 212b. Here, the optimal combination of design parameters may refer to the combination of design parameters that maximizes the number of I / O ports, is easiest to manufacture, or meets other process objectives.

[0025] Referring to Figure 1, in block S130, a plurality of second stacked structures 20 are provided, wherein the plurality of second stacked structures 20 are formed by bonding processes under different process conditions. Each of the plurality of second stacked structures 20 is formed by stacking and bonding a plurality of wafers (e.g., a third wafer W3 and a fourth wafer W4). The third wafer W3 has the same structure as the aforementioned first wafer W1, and the fourth wafer W4 has the same structure as the aforementioned second wafer W2, which will not be described in detail here.

[0026] In some embodiments, the process conditions for the bonding process may include bonding temperature, bonding accuracy (or bonding offset), RF power used in the surface treatment process of the bonding pads before bonding, or other process parameters. For example, in FIG8, the third wafers W3 and fourth wafers W4 of the plurality of second stacked structures 20 can be planned to offset during bonding, such that the bonding pads 112 of the third wafer W3 (including bonding pads 112a located in the first die region DR1 and bonding pads 112b located in the plurality of bonding test regions TR1) and the corresponding bonding pads 212 of the fourth wafer W4 (including bonding pads 212a located in the second die region DR2 and bonding pads 212b located in the plurality of bonding test regions TR2) are offset by a distance s1 (i.e., bonding offset) in the horizontal direction (e.g., the x-direction or y-direction). In some embodiments, the bonding offset can be in the range of 0 to 10% of the size of the bonding pads 112, 212. In some embodiments, the range of the bonding offset is limited to the resistance value being within specifications. In some embodiments, the plurality of second stacked structures 20 are formed by bonding the third wafer W3 and the fourth wafer W4 at different bonding temperatures. In some embodiments, the plurality of second stacked structures 20 are formed by bonding the third wafer W3 and the fourth wafer W4 under different surface treatment conditions.

[0027] Please refer to Figure 1. In block S140, electrical measurements, such as resistance measurements or other electrical measurements, are performed on the test lines C1 of the multiple junction test areas TR of the multiple second stacked structures 20.

[0028] Referring to Figure 1, in block S150, the process window for the bonding process of forming the first stacked structure 10 is determined by the results of electrical measurements of multiple second stacked structures 20. In some embodiments, the measured resistance values ​​and corresponding process parameters can be plotted to determine the process window of the process parameters. For example, in Figure 9, a graph showing the relationship between bonding offset and bonding pad spacing can be plotted under the condition that the design parameters of some bonding pads and the bonding process parameters are fixed. In Figure 9, the area marked by the diagonal line is the area where the measured resistance value is within the target range. That is, bonding pads 112 and 212 with spacing within the diagonal line area are allowed to offset within the corresponding bonding offset range. For example, in Figure 10, a graph showing the relationship between bonding temperature and bonding pad spacing can be plotted under the condition that the design parameters of some bonding pads and the bonding process parameters are fixed. In Figure 10, the area marked by the diagonal lines represents the region where the measured resistance value falls within the target range. This means that bonding pads 112 and 212 with a spacing within this diagonal line region are permissible to be bonded within the corresponding bonding temperature range. The above example is intended to clearly illustrate how the process window for the bonding process can be determined based on the results of electrical measurements, and is not intended to limit the invention. It should be understood that the numerical ranges for the spacing, bonding offset, and bonding temperature described above are merely illustrative and not intended to limit the invention. Similarly, graphs showing the relationship between the design parameters of other bonding pads, bonding process parameters, and resistance values ​​can be plotted to obtain the process window for each bonding process parameter.

[0029] In some embodiments, based on current process conditions and industry needs (e.g., number of input / output (I / O), cost considerations, space considerations, process capabilities, etc.), the combination of bonding process parameters of the first stacked structure 10 can be optimized through a process window of bonding process parameters obtained from multiple second stacked structures 20 tests.

[0030] Referring to Figure 1, in block S160, a plurality of third stacked structures 30 are provided, each of which is formed by stacking a different number of wafers. As shown in Figure 11, each of the plurality of third stacked structures 30 includes a bottom wafer WB, a top wafer WT, and at least one intermediate wafer WM. At least one intermediate wafer WM is disposed between the bottom wafer WB and the top wafer WT. The bottom wafer WB may have the same structure as the aforementioned first wafer W1, and the top wafer WT may have the same structure as the aforementioned second wafer W2, for example, which will not be described in detail here. The intermediate wafer WM may be a memory wafer, for example, similar to the aforementioned second wafer W2, except that bonding pads 312 and 314 are provided on both opposite sides of the intermediate wafer WM to correspondingly bond with the bonding pads of the wafers disposed on and below it. For clarity, Figure 11 only schematically illustrates the connections between bonding pads (including bonding pads 312, 314, 112, 212) of adjacent wafers in the bonding test area TR, and the test line C1, omitting other components inside each wafer. Furthermore, in the bonding test area TR of the third stack structure 30, the intermediate wafer WM also includes a conductive connector 316 located between bonding pads 312 and 314 to electrically connect bonding pads 312 and 314, forming part of the test line C1. In Figure 11, the conductive connector 316 is schematically represented by a conductive post, but this is not intended to limit the invention; the conductive connector 316 can be any structure that electrically connects adjacent and corresponding bonding pads 312 and 314. Figure 11 schematically illustrates three intermediate wafers WM, but this is not intended to limit the invention; each of the plurality of third stack structures 30 may each include one to ten or more intermediate wafers WM.

[0031] Please refer to Figure 1. In block S170, electrical measurements, such as resistance measurements or other electrical measurements, are performed on the test lines C1 of the multiple junction test areas TR of the multiple third stacked structures 30.

[0032] Referring to Figure 1, in block S180, the number of wafers that can be stacked in the first stacking structure 10 is determined by the results of electrical measurements of multiple third stacking structures 30. In some embodiments, the measured resistance values ​​and the corresponding number of wafers can be plotted to determine the number of wafers that can be stacked in the first stacking structure 10. Taking Figure 12 as an example, a graph showing the relationship between the number of wafers stacked and the resistance value can be plotted under the condition that the design parameters of the bonding pads and the bonding process parameters are fixed. In Figure 12, when the number of wafers stacked is between 1 and 5, the measured resistance value is within the target range; when the number of wafers stacked exceeds 5, the measured resistance value is outside the target range. It can be seen that under the condition that the design parameters of the bonding pads and the bonding process parameters are fixed, the first stacking structure 10 can stack a maximum of 5 layers of wafers. The above examples are intended to clearly illustrate how the number of wafers that can be stacked in the first stacking structure 10 can be determined by the results of electrical measurements of multiple third stacking structures 30, and are not intended to limit the present invention. It should be understood that the numerical range of the number of wafers stacked mentioned above is for illustrative purposes only and is not intended to limit the present invention.

[0033] In this way, the feasibility of including different numbers of stacked wafers in the first stacked structure 10 can be inferred through the electrical test results of the third stacked structure 30, and corresponding design modifications can be made in a timely manner. For example, if it is desired that the first stacked structure 10 includes more stacked wafers than the above-mentioned stackable number of wafers, the number of stacked wafers can be increased by reducing the height of the bonding layer (including bonding pads and / or bonding vias) of each wafer or increasing the spacing of the bonding pads to reduce the resistance value.

[0034] In summary, the stacked structure of the present invention, by setting multiple bonding test areas in the dicing channel, can perform electrical measurements on the test circuits of multiple bonding test areas to determine the feasible range of design parameters of bonding pads, bonding process parameters and number of wafers stacked in the stacked structure, and adjust the design of bonding layers in the stacked structure based on the obtained feasible ranges without affecting the layout design of the die region in the stacked structure. This can effectively reduce design costs and provide a design basis for further miniaturization or changes of the future stacked structure.

[0035] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0036] Figure 1 is a flowchart of a design method for a bonding layer of a stacked structure according to an embodiment of the present invention. Figure 2 is a cross-sectional schematic diagram of a first stacked structure according to an embodiment of the present invention. Figure 3 is a cross-sectional schematic diagram of a bonding test area according to an embodiment of the present invention. Figure 4 is a top view of the first wafer of the first stacked structure of Figure 2 at the bonding interface. Figure 5 is a top view of the second wafer of the first stacked structure of Figure 2 at the bonding interface. Figures 6A to 6C are top views of some embodiments of bonding pads. Figure 7 is a graph showing the relationship between the spacing and shape of bonding pads and the resistance value. Figure 8 is a cross-sectional schematic diagram of a bonding test area according to another embodiment of the present invention. Figure 9 is a graph showing the relationship between bonding offset and bonding pad spacing. Figure 10 is a graph showing the relationship between bonding temperature and bonding pad spacing. Figure 11 is a cross-sectional schematic diagram of a bonding test area according to another embodiment of the present invention. Figure 12 is a graph showing the relationship between the number of wafers stacked and the resistance value.

Claims

1. A design method for a bonding layer in a stacked structure, comprising: A first stacked structure is provided, the first stacked structure being formed by stacking and bonding multiple wafers, wherein the first stacked structure has multiple die regions, multiple bonding test regions, and dicing channels, the dicing channels separating the multiple die regions, and the multiple bonding test regions being located in the dicing channels, wherein each of the multiple bonding test regions of the first stacked structure includes a test line, the test line of the first stacked structure including a conductive bonding structure formed by bonding pads of the multiple wafers bonding with each other, wherein the bonding pads of the multiple wafers of the first stacked structure in each of the multiple bonding test regions have different design parameters; electrical measurements are performed on the test lines of the multiple bonding test regions of the first stacked structure respectively; and the range of available design parameters for the bonding pads in the multiple die regions of the first stacked structure is determined by the results of the electrical measurements.

2. A method for designing the bonding layer of a stacked structure as described in claim 1, wherein the design parameters of the bonding pads include shape, size, and / or spacing.

3. A method for designing a bonding layer of a stacked structure as described in claim 1, wherein the first stacked structure comprises: A first wafer includes: a plurality of first grain regions; a first dicing kerf separating the plurality of first grain regions; and a plurality of first bonding test regions located within the first dicing kerf, wherein the plurality of first bonding test regions include a first region and a second region, the first region including a plurality of first bonding pads, and the second region including a plurality of second bonding pads; and a second wafer includes: a plurality of second grain regions; a second dicing kerf separating the plurality of second grain regions; and a plurality of second bonding test regions located within the second dicing kerf, wherein the plurality of second bonding test regions include a third region and a fourth region, the third region including a plurality of third bonding pads, and the fourth region including a plurality of fourth bonding pads. The bonding pads in the plurality of second grain regions of the second wafer are bonded to the corresponding bonding pads in the plurality of first grain regions of the first wafer, the plurality of third bonding pads in the third region of the second wafer are bonded to the plurality of first bonding pads in the first region of the first wafer to form a first test circuit, and the plurality of fourth bonding pads in the fourth region of the second wafer are bonded to the plurality of second bonding pads in the second region of the first wafer to form a second test circuit.

4. A method for designing a bonding layer of a stacked structure as described in claim 3, wherein the plurality of first bonding pads and the plurality of third bonding pads have substantially the same shape, size and spacing, and the plurality of second bonding pads and the plurality of fourth bonding pads have substantially the same shape, size and spacing.

5. A method for designing a bonding layer of a stacked structure as described in claim 3, wherein the first test line travels between the first region of the first wafer and the third region of the second wafer, and the second test line travels between the second region of the first wafer and the fourth region of the second wafer.

6. A method for designing a bonding layer of a stacked structure as described in claim 3, wherein when the electrical performance of the first test line is within a target range, the design parameters of the plurality of first bonding pads or the plurality of third bonding pads are applicable to the bonding pads of the plurality of first grain regions or the plurality of second grain regions.

7. A method for designing the bonding layer of a stacked structure as described in claim 3, wherein the second bonding test area further comprises: A second conductive layer is disposed on the plurality of third bonding pads; And a second conductive via is disposed between the second conductive layer and the plurality of third bonding pads to electrically connect the second conductive layer and the plurality of third bonding pads, wherein the first bonding test area further includes: a first conductive layer disposed on the plurality of first bonding pads; A first conductive via is disposed between the first conductive layer and the plurality of first bonding pads to electrically connect the first conductive layer and the plurality of first bonding pads. The first test circuit is composed of the first conductive layer, the first conductive via, the plurality of first bonding pads, the plurality of second bonding pads, the second conductive via, and the second conductive layer.

8. The method for designing the bonding layer of the stacked structure as described in claim 1 further includes: Provide a plurality of second stacked structures, each of the plurality of second stacked structures being formed by stacking and bonding a third wafer and a fourth wafer, wherein the plurality of second stacked structures are formed by bonding processes under different process conditions; perform electrical measurements on the test lines of a plurality of bonding test areas of the plurality of second stacked structures respectively; and determine the process window of the bonding process of the first stacked structure by means of the results of the electrical measurements of the plurality of second stacked structures.

9. A method for designing a bonding layer of a stacked structure as described in claim 8, wherein the process conditions include bonding temperature, bonding offset, and radio frequency power for pretreatment of the bonding pad surface.

10. The method for designing the bonding layer of the stacked structure as described in claim 1, further comprising: Provide multiple third stacked structures, each of which is formed by stacking and bonding different numbers of wafers; perform electrical measurements on the test lines of multiple bonding test areas of the multiple third stacked structures respectively; and determine the range of the number of wafers that can be stacked in the first stacked structure by means of the results of the electrical measurements of the multiple third stacked structures.

11. A stacked structure, comprising: A first wafer includes: a plurality of first grain regions; a first dicing kerf separating the plurality of first grain regions; and a plurality of first bonding test regions located in the first dicing kerf, wherein the plurality of first bonding test regions include a first region and a second region, the first region including a plurality of first bonding pads, and the second region including a plurality of second bonding pads; and a second wafer includes: a plurality of second grain regions; a second dicing kerf separating the plurality of second grain regions; and a plurality of second bonding test regions located in the second dicing kerf, wherein the plurality of second bonding test regions include a third region and a fourth region, the third region including a plurality of third bonding pads, and the fourth region including a plurality of fourth bonding pads, wherein the bonding pads in the plurality of second grain regions of the second wafer are in direct contact with corresponding bonding pads in the plurality of first grain regions of the first wafer, the plurality of third bonding pads in the third region of the second wafer are in direct contact with the plurality of first bonding pads in the first region of the first wafer, and the plurality of fourth bonding pads in the fourth region of the second wafer are in direct contact with the plurality of second bonding pads in the second region of the first wafer. The design parameters of the plurality of first bonding pads are different from the design parameters of the plurality of second bonding pads.

12. The stacked structure as claimed in claim 11, wherein the shape of the plurality of first bonding pads is different from the shape of the plurality of second bonding pads.

13. The stacked structure as claimed in claim 11, wherein the dimensions of the plurality of first bonding pads are different from the dimensions of the plurality of second bonding pads.

14. The stacking structure as claimed in claim 11, wherein the spacing of the plurality of first bonding pads is different from the spacing of the plurality of second bonding pads.

15. The stacking structure as described in claim 11, further comprising: The first test circuit travels between the first region of the first wafer and the third region of the second wafer; And a second test circuit, traveling between the second region of the first wafer and the fourth region of the second wafer.

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