Chip on film package structure

Abstract

A chip on film package structure including a flexible substrate, a patterned circuit layer, a chip, a plurality of wires and an encapsulant is provided. The flexible substrate has a chip mounting area. The patterned circuit layer is disposed on the flexible substrate and includes a plurality of first leads and a plurality of second leads. Each of the first leads has a first inner lead extending into the chip mounting area. The second leads are located outside the chip mounting area and each has a contact portion. The chip is electrically connected to the patterned circuit layer. The chip includes an upper surface, a lower surface, a plurality of bumps and a plurality of pads. The bumps are disposed on the lower surface, and the pads are disposed on the upper surface. The bumps are respectively connected to the first inner leads. The wires connect the pads and the contact portions respectively. The encapsulant is disposed on the flexible substrate and covers the chip and the wires.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a thin-film flip-chip packaging structure. Prior Technology

[0002] Chip-on-Film (COF) packaging uses flip-chip bonding to mount a chip within a chip mounting area of ​​a flexible substrate and electrically connect it to circuitry on the flexible substrate. Multiple signal sources from the chip extend through multiple bumps on the chip to multiple internal pins within the chip mounting area to receive and transmit signals. Due to the limited space within the chip mounting area, the number of internal pins that can extend into the chip mounting area is limited, preventing the chip from expanding the number of signal input / output endpoints and thus limiting the performance improvement of the COF packaging structure. Summary of the Invention

[0003] This invention provides a thin-film flip-chip packaging structure with superior performance.

[0004] The thin-film flip-chip packaging structure of the present invention includes a flexible substrate, a patterned circuit layer, a wafer, a plurality of conductive lines, and an encapsulating adhesive layer. The flexible substrate has a first surface and a second surface opposite to each other, and a wafer mounting region located on the first surface. The patterned circuit layer is disposed on the first surface of the flexible substrate. The patterned circuit layer includes a plurality of first lines and a plurality of second lines. Each of the first lines has a first inner pin extending into the wafer mounting region, and each of the second lines is located outside the wafer mounting region and has a contact. The wafer is disposed within the wafer mounting region and electrically connected to the patterned circuit layer. The wafer includes an upper surface, a lower surface, a plurality of bumps, and a plurality of pads. The bumps are disposed on the lower surface, and the pads are disposed on the upper surface. The bumps are respectively connected to the first inner pins of the first lines. The conductive lines are respectively connected to the pads and the contacts of the second lines. The encapsulating adhesive layer is disposed on the first surface of the flexible substrate and covers the wafer and the conductive lines.

[0005] Based on the above, the chip in the thin-film flip-chip packaging structure of the present invention is connected to the first internal pin of the first line located within the chip mounting area via bumps disposed on the lower surface of the chip, and is connected to the second line located outside the chip mounting area via wires via pads disposed on the upper surface of the chip. In this way, the number of endpoints for receiving and outputting signals can be increased without increasing the chip size, and signal transmission can be performed through the first line within the chip mounting area and the second line outside the chip mounting area. Since the second line does not extend into the chip mounting area, it is not limited by the limited wiring space of the chip mounting area, allowing full utilization of the space on the flexible substrate, thereby improving the space utilization, wiring flexibility, and performance of the thin-film flip-chip packaging structure. Simple Explanation of the Diagram

[0006] Figure 1A is a top view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 1B is a partially enlarged view of the thin-film flip-chip packaging structure of Figure 1A. Figure 1C is a partially enlarged view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view of the thin-film flip-chip packaging structure of Figure 1A along the A-A' section. Figure 3 is a cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 4 is a cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 5 is a cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 6 is a cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Implementation

[0007] Figure 1A is a top view of a thin-film flip-chip package structure according to an embodiment of the present invention. Figure 1B is a partially enlarged view of the thin-film flip-chip package structure of Figure 1A. Figure 1C is a partially enlarged view of the thin-film flip-chip package structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view of the thin-film flip-chip package structure of Figure 1A along section line A-A'. It should be noted that the thin-film flip-chip package structure 100 in Figure 1A is the appearance of the whole roll tape transport operation stage, and only one thin-film flip-chip package structure 100 is schematically shown. The components covered by the encapsulating adhesive layer 160 in Figure 1A are shown with solid lines to facilitate component description. Referring to Figures 1A to 2 simultaneously, the thin-film flip-chip package structure 100 includes a flexible substrate 110, a patterned circuit layer 120, a wafer 140, a plurality of conductive lines 150, and an encapsulating adhesive layer 160. The flexible substrate 110 has a first surface 113 and a second surface 114 opposite to each other, and a wafer placement area 112 located on the first surface 113. A patterned circuit layer 120 is disposed on the first surface 113 of the flexible substrate 110. A wafer 140 is disposed in the wafer setting area 112 and electrically connected to the patterned circuit layer 120.

[0008] The patterned circuit layer 120 includes a plurality of first lines 121 and a plurality of second lines 122. Each of the first lines 121 has a first internal pin 121a extending into the wafer mounting region 112, and each of the second lines 122 is located outside the wafer mounting region 112 and has a contact 122a. The wafer 140 includes an upper surface 141, a lower surface 142, a plurality of bumps 143, and a plurality of pads 144. The bumps 143 are disposed on the lower surface 142, and the pads 144 are disposed on the upper surface 141. The bumps 143 are respectively connected to the first internal pins 121a of the first lines 121. The wires 150 are respectively connected to the pads 144 and the contacts 122a of the second lines 122. In detail, the wafer 140 may, for example, connect the first lines 121 by thermocompression bonding, such that the bumps 143 and the first internal pins 121a are eutectic bonded. These wires 150 can be electrically connected, for example, by wire bonding, to the contacts 122a of the second lines 122. The multiple signal sources of the chip 140 receive and transmit signals through the bumps 143 and the contacts 144.

[0009] An encapsulating adhesive layer 160 is disposed on the first surface 113 of the flexible substrate 110 and covers the wafer 140 and the conductive lines 150 to protect the conductive lines 150 and the electrical connection endpoints of the conductive lines 150 with the pads 144 and the contacts 122a, ensuring stable transmission of electrical signals between the pads 144 and the second line 122. The flexible substrate 110 includes a predetermined bending region 111, and the encapsulating adhesive layer 160 is located outside the predetermined bending region 111 to avoid affecting the bending freedom of the thin-film flip-chip package structure 100 in subsequent applications. In this embodiment, there are two predetermined bending regions 111, and the encapsulating adhesive layer 160 is located between the two predetermined bending regions 111.

[0010] As shown in Figure 1A, the first lines 121 extend away from the wafer mounting region 112 and each has a first external pin 121b relative to the first internal pin 121a. The second lines 122 extend away from the wafer mounting region 112 and each has a second external pin 122b relative to the contact 122a. The thin-film flip-chip package structure 100 further includes a solder resist layer 130. The solder resist layer 130 is disposed on the first surface 113 of the flexible substrate 110 and partially covers the patterned circuit layer 120. The solder resist layer 130 includes a first opening 131 and a plurality of second openings 132. The first opening 131 exposes the wafer mounting region 112, and the second openings 132 expose the contacts 122a of the second lines 122, so that one end 151 of the conductors 150 can be connected to the contacts 122a. The solder mask 130 further exposes the first external leads 121b and the second external leads 122b for subsequent electrical bonding to other external components. An encapsulating adhesive layer 160 covers the second openings 132. That is, the electrical connection points 122a exposed by these second openings 132 to one end 151 of the wires 150 are covered by the encapsulating adhesive layer 160 to prevent damage or contamination.

[0011] As shown in Figure 1B, in this embodiment, the contact 122a of the second line 122 is located in the middle of the second line 122 rather than at its end. That is, the second line 122 is partially covered by the solder resist layer 130 on both opposite sides of the contact 122a. The width of the contact 122a is greater than the width of the other parts of the second line 122. The shape of the contact 122a corresponds to the shape of the second opening 132 and is rectangular, but is not limited thereto. In an embodiment not shown, the width of the contact 122a may be equal to the width of the other parts of the second line 122. In an embodiment not shown, the shape of the contact 122a may be any polygon or circle. As shown in Figure 1C, in other embodiments, the contact 122a' of the second line 122 may also be located at the end of the second line 122. That is, the second line 122 is covered by the solder resist layer 130 only on one side of the contact 122a'. The width of contact 122a' is greater than the width of other parts of the second line 122 outside of contact 122a', but is not limited thereto.

[0012] As shown in Figure 2, the thin-film flip-chip package structure 100 further includes an underfill adhesive 170. The underfill adhesive 170 fills at least between the lower surface 142 of the wafer 140 and the first surface 113 of the flexible substrate 110, and covers the wafer mounting area 112 to protect the electrical contacts of the bumps 143 and the first internal pins 121a of the wafer 140. An encapsulating adhesive layer 160 covers the underfill adhesive 170.

[0013] In this embodiment, the chip 140 of the thin-film flip-chip package structure 100 can not only be electrically connected to the first internal pin 121a located in the chip mounting area 112 through the bumps 143 disposed on the lower surface 142, but can also be further electrically connected to the pads 144 disposed on the upper surface 141 to the second line 122 located outside the chip mounting area 112 through the wires 150. This allows the chip 140 to increase the number of endpoints for receiving and outputting signals without increasing its size, thereby improving the performance of the thin-film flip-chip package structure 100. In addition, since these second lines 122 are located outside the chip mounting area 112, they are not limited by the limited wiring space within the chip mounting area 112, allowing the space on the flexible substrate 110 to be fully utilized, thereby improving the space utilization and wiring flexibility of the thin-film flip-chip package structure 100.

[0014] Figure 3 is a cross-sectional view of a thin-film flip-chip package structure according to an embodiment of the present invention. Referring to Figures 2 and 3 simultaneously, the thin-film flip-chip package structure 100a of this embodiment is similar to the aforementioned embodiment, except that the thin-film flip-chip package structure 100a of this embodiment further includes a heat dissipation element 180a to assist in dissipating the heat generated during operation. The heat dissipation element 180a is disposed on the first surface 113 of the flexible substrate 110 and at least partially covers the encapsulating adhesive layer 160. In this embodiment, the heat dissipation element 180a completely covers the encapsulating adhesive layer 160 and partially covers the solder resist layer 130, but is not limited thereto. The types of heat dissipation element 180a may include, but are not limited to, thermal paste, thermal film, and heat sink. As the number of signal receiving and output terminals of the chip 140 increases, the chip 140 generates more heat during operation. Therefore, the heat dissipation element 180a in this embodiment can improve the heat dissipation effect of the thin-film flip-chip package structure 100a to avoid structural damage or electrical abnormalities caused by excessive temperature.

[0015] Figure 4 is a cross-sectional view of a thin-film flip-chip package structure according to an embodiment of the present invention. Referring simultaneously to Figures 3 and 4, the thin-film flip-chip package structure 100b of this embodiment is similar to that of the aforementioned embodiments, except that the heat dissipation element 180b in this embodiment partially covers the encapsulating adhesive layer 160. Specifically, the heat dissipation element 180b only covers the top surface 161 of the encapsulating adhesive layer 160, but is not limited thereto. The top surface 161 corresponds to the upper surface 141 of the wafer 140. The thin-film flip-chip package structure 100b of this embodiment has similar effects to the aforementioned embodiments, and will not be described again here.

[0016] Figure 5 is a cross-sectional view of a thin-film flip-chip package structure according to an embodiment of the present invention. Referring simultaneously to Figures 3 and 5, the thin-film flip-chip package structure 100c of this embodiment is similar to that of the aforementioned embodiments, except that the heat dissipation element 180c of this embodiment is disposed on the second surface 114 of the flexible substrate 110 and at least corresponds to the wafer mounting area 112. The thin-film flip-chip package structure 100c of this embodiment has similar effects to the aforementioned embodiments, and will not be described again here.

[0017] Figure 6 is a cross-sectional view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Referring simultaneously to Figures 3 and 6, the thin-film flip-chip packaging structure 100d of this embodiment is similar to the aforementioned embodiment, except that the number of heat dissipation elements in this embodiment is two. One heat dissipation element 180d is disposed on the first surface 113 of the flexible substrate 110 and covered by the encapsulating adhesive layer 160, and the other heat dissipation element 180e is disposed on the second surface 114 of the flexible substrate 110. The thin-film flip-chip packaging structure 100d of this embodiment has similar effects to the aforementioned embodiment, and will not be described again here.

[0018] In summary, the chip in the thin-film flip-chip packaging structure of the present invention is connected to the first internal pin of the first line located within the chip mounting area via bumps disposed on the lower surface of the chip, and is connected to the second line located outside the chip mounting area via wires via pads disposed on the upper surface of the chip. This allows for an increase in the number of endpoints for receiving and outputting signals without increasing the chip size, and enables signal transmission via the first line within the chip mounting area and the second line outside the chip mounting area. Since the second line does not extend into the chip mounting area, it is not limited by the limited wiring space of the chip mounting area, allowing for full utilization of the space on the flexible substrate, thereby improving the space utilization, wiring flexibility, and performance of the thin-film flip-chip packaging structure.

[0019] A-A': section line 100, 100a, 100b, 100c, 100d: Thin-film flip-chip packaging structure 110: Flexible substrate 111: Pre-ordered bending area 112: Chip Setup Area 113: First Surface 114: Second Surface 120: Patterned Circuit Layer 121: Route 1 121a: First internal pin 121b: First external pin 122: Second Route 122a, 122a': Contact 122b: Second external pin 130: Solder resist layer 131: First opening 132: Second opening 140: Chip 141: Upper surface 142: Lower surface 143: Bump 144: Connecting pad 150: Wire 151: End 160: Encapsulating adhesive layer 161: Top surface 170: Bottom filler glue 180a, 180b, 180c, 180d, 180e: Heat dissipation components

Claims

1. A thin-film flip-chip packaging structure, comprising: A flexible substrate has a first surface and a second surface opposite to each other and a wafer mounting area located on the first surface; A patterned circuit layer is disposed on the first surface of the flexible substrate. The patterned circuit layer includes a plurality of first lines and a plurality of second lines. Each of the first lines has a first inner pin extending into the wafer mounting area. The second lines are located outside the wafer mounting area and each has a contact. A wafer is disposed in the wafer mounting area and electrically connected to the patterned circuit layer. The wafer includes an upper surface, a lower surface, a plurality of bumps, and a plurality of pads. The bumps are disposed on the lower surface, and the pads are disposed on the upper surface. The bumps are respectively connected to the first inner pins of the first lines. A plurality of wires are respectively connected to the pads and the contacts of the second lines. An encapsulating adhesive layer is disposed on the first surface of the flexible substrate and covers the wafer and the conductive lines; and a solder resist layer is disposed on the first surface of the flexible substrate and partially covers the patterned circuit layer, the solder resist layer including a first opening and a plurality of second openings, the first opening exposing the wafer mounting area, and the second openings respectively exposing the contacts of the second circuits.

2. The thin-film flip-chip package structure as claimed in claim 1, wherein the first lines extend in a direction away from the wafer mounting area and each has a first external pin relative to the first internal pin, the second lines extend in a direction away from the wafer mounting area and each has a second external pin relative to the contact, and the solder mask exposes the first external pins and the second external pins.

3. The thin-film flip-chip encapsulation structure as claimed in claim 1, wherein the encapsulating adhesive layer covers the second openings.

4. The thin-film flip-chip packaging structure as claimed in claim 1 further includes an underfill adhesive, the underfill adhesive filling at least between the lower surface of the wafer and the first surface of the flexible substrate and covering the wafer mounting area.

5. The thin-film flip-chip packaging structure as claimed in claim 1, wherein the flexible substrate includes a predetermined bending region, and the encapsulating adhesive layer is located outside the predetermined bending region.

6. The thin-film flip-chip packaging structure as claimed in claim 1 further includes a heat dissipation element disposed on the first surface of the flexible substrate and at least partially covering the encapsulation adhesive layer.

7. The thin-film flip-chip packaging structure as described in claim 6, wherein the heat dissipation element includes heat dissipation adhesive, heat dissipation film and heat sink.

8. The thin-film flip-chip packaging structure as claimed in claim 1 further includes a heat dissipation element disposed on the second surface of the flexible substrate and at least corresponding to the wafer mounting area.

9. The thin-film flip-chip packaging structure as described in claim 8, wherein the heat dissipation element includes heat dissipation adhesive, heat dissipation film and heat sink.

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