Semiconductor substrate and its preparation method

Abstract

The present invention provides a semiconductor substrate and a method for preparing the same. The method includes: heat-treating a nitrogen-doped silicon substrate to diffuse nitrogen from the silicon substrate to the surface of the silicon substrate, thereby forming nucleation sites of a predetermined size on the surface of the silicon substrate by the nitrogen; and growing a polycrystalline silicon thin film on the nucleation sites to form a semiconductor substrate.

Description

Technical Field

[0001] Cross-reference of related applications

[0002] This invention claims priority to Chinese Patent Application No. 202511339371.7, filed in China on September 18, 2025, the entire contents of which are incorporated herein by reference.

[0003] This invention relates to the field of semiconductor materials technology, and more particularly to semiconductor substrates and their preparation methods. Prior Technology

[0004] In modern information technology and electronic systems, radio frequency (RF) integrated circuits play a fundamental role as key components for achieving efficient message transmission, reception, and processing. Their applications are wide-ranging, including communication systems such as smartphones, Wi-Fi, Bluetooth, and GPS, as well as non-communication scenarios such as radar, medical imaging, industrial sensing, and Internet of Things (IoT) devices.

[0005] In achieving the aforementioned high-performance radio frequency (RF) functions, the selection of materials and the control of performance of the semiconductor substrate, which serves as the carrier of RF integrated circuits, are crucial. The electrical properties of the substrate, including its resistivity, dielectric constant, and ability to suppress parasitic effects, directly determine the high-frequency response, signal integrity, power efficiency, and long-term operational stability of the integrated components on it.

[0006] Currently widely used high-resistivity silicon substrates can meet the performance requirements at low and medium frequencies to a certain extent. However, in high-frequency, low-power, and high-linearity radio frequency systems, their ability to suppress surface parasitic conductivity and maintain high effective resistivity is gradually showing technical bottlenecks. As radio frequency circuits develop towards higher frequencies, wider bandwidths, and stronger environmental adaptability, traditional silicon substrates can no longer fully meet the comprehensive requirements of next-generation radio frequency integrated circuits for extreme performance and high reliability. Summary of the Invention

[0007] In view of this, the present invention provides a semiconductor substrate and a method for fabricating the same. This method involves heat-treating a nitrogen-doped silicon substrate to form nucleation sites of controllable size and density on the surface, guiding the growth of a polycrystalline silicon thin film with corresponding grain characteristics. This allows for precise control of the semiconductor substrate's microstructure and the construction of a stable and efficient carrier trapping layer, enabling it to maintain high resistivity and excellent isolation performance even during high-temperature processes.

[0008] The technical solution of this invention is implemented as follows:

[0009] In a first aspect, the present invention provides a method for preparing a semiconductor substrate, the method comprising:

[0010] A nitrogen-doped silicon substrate is heat-treated to allow nitrogen to diffuse to the surface of the substrate, thereby forming nucleation sites with a predetermined size and / or density on the surface of the substrate.

[0011] Polycrystalline silicon thin films are grown at nucleation sites to form semiconductor substrates.

[0012] In some examples, growing polycrystalline silicon films at nucleation sites includes:

[0013] Seed layers are formed at the nucleation sites;

[0014] A polycrystalline silicon layer is grown on the seed layer.

[0015] In some examples, the nitrogen doping concentration in the silicon substrate is greater than 1E18atom / cm3.

[0016] In some examples, the heat treatment is a rapid heat treatment at 600°C to 1000°C.

[0017] In some examples, the size of the nucleation sites is in the range of 20–40 nm, and the grain size of the polycrystalline silicon film is in the range of 80–120 nm.

[0018] In some examples, the difference between the maximum and minimum grain size in polycrystalline silicon films is less than 50% of their average grain size.

[0019] In some examples, the step of forming the seed layer includes: performing a heat treatment at a temperature of 900°C for 10 minutes to form the seed layer with a grain size in the range of 20 to 40 nm.

[0020] In some examples, the step of growing a polycrystalline silicon layer on a seed layer includes: performing a heat treatment at a temperature of 950°C for 30 minutes to form a polycrystalline silicon layer with a grain size in the range of 80 to 120 nm.

[0021] In some examples, the steps for growing polycrystalline silicon films include growing polycrystalline silicon films using atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0022] In some examples, the growth of polycrystalline silicon thin films is carried out at a temperature of 400–1000 °C for 10–60 minutes.

[0023] In some examples, the resistivity of the semiconductor substrate is greater than 1000 ohm-cm, and the resistivity of the polycrystalline silicon thin film is greater than 1000 ohm-cm.

[0024] In some examples, the preparation method further includes:

[0025] Pulling nitrogen-doped single-crystal silicon rods;

[0026] Nitrogen-doped silicon substrates are obtained by cutting single-crystal silicon rods.

[0027] In a second aspect, the present invention provides a semiconductor substrate, comprising:

[0028] Nitrogen-doped silicon substrates; and

[0029] A polycrystalline silicon thin film disposed on a silicon substrate;

[0030] Among them, the average grain size of polycrystalline silicon thin films is in the range of 80~120 nm, and the difference between the maximum and minimum grain size in polycrystalline silicon thin films is less than 50% of the average grain size.

[0031] In some examples, the polycrystalline silicon thin film includes: a seed layer formed on a silicon substrate; and a polycrystalline silicon layer formed on the seed layer.

[0032] In some examples, the nitrogen doping concentration in the silicon substrate is greater than 1E18atom / cm3.

[0033] In some examples, the average grain size of the seed layer is in the range of 20–40 nm.

[0034] In some examples, the resistivity of the silicon substrate is greater than 1000 ohm-cm, and the resistivity of the polycrystalline silicon thin film is greater than 1000 ohm-cm.

[0035] This invention provides a semiconductor substrate and its fabrication method. The method involves heat-treating a nitrogen-doped silicon substrate, causing nitrogen to diffuse onto the substrate surface, thereby forming nucleation sites of predetermined size, upon which a polycrystalline silicon thin film is grown. This method not only utilizes the nitrogen-generated nucleation sites to form a small and uniform grain structure in the early stages of polycrystalline silicon growth, but also effectively suppresses grain growth through the pinning effect of nitrogen atoms on grain boundaries during subsequent growth, thus achieving precise control over the microstructure of the polycrystalline silicon thin film. The resulting high-density grain boundaries constitute numerous carrier traps within the semiconductor substrate, effectively capturing and recombinizing free carriers excited under high-frequency electric fields, thereby significantly improving the effective resistivity and isolation performance of the semiconductor substrate, laying the foundation for the fabrication of high-performance radio frequency integrated circuits. Simple Explanation of the Diagram

[0036] Figure 1 is a flowchart of the semiconductor substrate preparation method provided in an embodiment of the present invention.

[0037] Figure 2 is a process flow diagram of the semiconductor substrate fabrication method provided in the embodiment of the present invention.

[0038] Figure 3 is a process flow diagram of a semiconductor substrate fabrication method provided in some other embodiments of the present invention.

[0039] Figure 4 is a schematic diagram of the semiconductor substrate provided in an embodiment of the present invention.

[0040] Figure 5 shows a microscopic image of a nitrogen-free seed layer on a semiconductor substrate.

[0041] Figure 6 shows a microscopic image of a nitrogen-containing seed layer on a semiconductor substrate.

[0042] Figure 7 shows a microscopic image of a nitrogen-free polycrystalline silicon layer on a semiconductor substrate.

[0043] Figure 8 shows a microscopic image of a nitrogen-containing polycrystalline silicon layer on a semiconductor substrate.

[0044] Figure 9 is a box plot showing the grain size in the nitrogen-containing seed layer and polycrystalline silicon layer of a semiconductor substrate compared to the grain size in the nitrogen-free seed layer and polycrystalline silicon layer. Implementation

[0045] The technical solution of the present invention will be clearly and completely described below with reference to the drawings in the present invention.

[0046] In the field of radio frequency (RF) integrated circuit manufacturing, with the rapid development of demands for high-speed message transmission, precise detection, and multifunctional integration, the operating frequency of integrated components is constantly increasing, and the system integration level is also showing a rapid upward trend. These technological developments have placed more stringent requirements on the substrate materials used to construct RF integrated circuits. Especially in the process of high-frequency signal transmission, how to effectively suppress inter-circuit interference, reduce signal transmission loss, and improve signal integrity has become one of the key factors affecting the performance of RF components.

[0047] While conventional high-resistivity silicon substrates can reduce parasitic conduction paths to some extent, they still have significant shortcomings under extremely high-frequency conditions. These shortcomings mainly manifest as a decrease in effective resistivity, insufficient isolation capability, and exacerbated substrate parasitic effects. These factors severely restrict the substrate's performance in high-frequency environments, preventing it from effectively meeting the signal quality and system stability requirements of integrated circuits.

[0048] Based on long-term tracking and in-depth analysis of the above-mentioned problems, the inventors have realized that one of the fundamental reasons for these performance bottlenecks is that under the action of a high-frequency electric field, free carriers, especially minority carriers, are easily excited in the substrate material. These carriers can migrate along the conductive path to non-target circuit regions, forming parasitic conduction channels or coupling paths, which in turn leads to signal interference and affects signal integrity and effective isolation between circuits.

[0049] Based on this, the inventors attempted to incorporate an insulating layer into the substrate or employ high resistivity doping methods. However, these methods still cannot effectively and stably restrict free carriers through physical mechanisms. Especially in actual manufacturing processes, the substrate often undergoes multiple rounds of high-temperature heat treatment (such as annealing, oxidation, alloying, etc.), which induce changes in the internal structure of the material, further weakening the already limited carrier suppression capability. Therefore, how to achieve precise intervention and long-term stable control of free carrier behavior from the microstructural level is the technical problem that the inventors aim to solve.

[0050] To systematically explore the physical essence of the aforementioned problems and their solutions, the inventors studied the excitation and migration of free charge carriers, starting from the mechanism of charge carrier movement in semiconductors. The research shows that the propagation path and recombination probability of free charge carriers are constrained by the local energy level structure and spatial barrier conditions, and are particularly sensitive to the distribution of microscopic defect states and grain boundaries. In polycrystalline or amorphous transition structures, the presence of numerous discontinuous lattice coordinations, stress distortions, and dangling bonds in the grain boundary regions creates natural trap states and energy level perturbations, which can significantly increase the recombination probability of charge carriers, thereby blocking the carrier diffusion channels.

[0051] Therefore, the inventors propose that by constructing a microstructure layer with high defect density, high grain boundary density, or high band distortion region in the substrate structure, it is possible to suppress high-frequency free carriers and improve the overall equivalent resistivity and isolation performance of the substrate without significantly changing the conductivity type of the substrate. Based on this concept, the inventors conducted multiple rounds of experimental verification focusing on the structural characteristics and thermal treatment response features of polycrystalline silicon materials, paying particular attention to the evolution of grain size and grain boundary density under different temperature and stress environments.

[0052] During the experiment, the inventors found that although the initially formed polycrystalline microstructure could meet the carrier suppression requirements in terms of grain boundary density, in subsequent high-temperature processes (such as annealing, oxidation, etc.), the microstructure showed a trend of significant grain growth and grain boundary merging, resulting in a rapid decrease in grain boundary density, degradation of trapping ability, and difficulty in maintaining its functional effectiveness in subsequent integration processes.

[0053] To address the aforementioned problems, this invention provides a semiconductor substrate and its fabrication method. This method involves heat-treating a nitrogen-doped silicon substrate to form high-density, uniformly sized nucleation sites on its surface, guiding the growth of a fine-grained, highly uniform polycrystalline silicon thin film. This effectively suppresses abnormal grain growth during subsequent high-temperature processes, thereby constructing a stable and efficient carrier trapping layer. This ensures that the semiconductor substrate maintains its high resistivity and excellent isolation performance even after undergoing complex high-temperature processes.

[0054] Referring to Figure 1, some embodiments of the present invention provide a method for preparing a semiconductor substrate, which may mainly include steps S01 and S02.

[0055] Referring to Figures 1 and 2, in step S01, the nitrogen-doped silicon substrate 100 is heat-treated to allow nitrogen to diffuse from the silicon substrate 100 to the surface of the silicon substrate 100, thereby forming nucleation sites SS of a predetermined size on the surface of the silicon substrate 100 by the nitrogen.

[0056] In step S02, a polycrystalline silicon thin film 10 is grown on the nucleation site SS to form a semiconductor substrate 1.

[0057] In summary, the core of this preparation method lies in utilizing specific elements pre-doped in a silicon substrate, which, under specific heat treatment conditions, are directionally diffused onto the surface of the silicon substrate, forming nucleation sites (SS) with specific microscopic characteristics (size and / or density) in situ on the surface. These nucleation sites (SS) are the basis for subsequent polycrystalline silicon thin film growth, and their characteristics directly determine the initial grain structure of the polycrystalline silicon thin film.

[0058] In the various embodiments of the present invention, a silicon substrate 100 is used as an example for illustration. However, those skilled in the art will understand that this principle can also be applied to other semiconductor materials, such as, but not limited to, silicon carbide (SiC) substrates, gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, etc.

[0059] To achieve effective diffusion of dopant elements and controllable formation of nucleation sites SS, the silicon substrate 100 can be pre-doped before heat treatment. That is, specific dopant elements are intentionally introduced during the growth process or subsequent fabrication of the silicon substrate 100. These dopant elements are not traditional elements used to adjust conductivity, but rather elements that the inventors have determined and specifically identified as capable of diffusing from the interior of the silicon substrate to its surface during heat treatment and reacting with the silicon substrate material or its surface environment to form independent and stable microscopic nucleation sites. In this invention, nucleation sites SS refer to microscopic regions formed on the surface of the silicon substrate that can serve as starting points for subsequent polycrystalline silicon thin film growth.

[0060] Through in-depth research into the nucleation mechanism, the inventors have realized that the formation of nucleation sites (SS) occurs because, under specific high-temperature heat treatment conditions, dopants inside the silicon substrate acquire sufficient activation energy and diffuse to the silicon substrate surface via lattice gaps or substitution mechanisms. When these diffused dopants reach a certain degree of supersaturation, they preferentially aggregate on the surface or undergo chemical reactions with surface atoms / environmental components, thereby forming new phase microregions with specific crystal structures or chemical compositions. These new phase microregions, due to their different surface energy, lattice matching degree, or chemical activity compared to the main surface of the silicon substrate, become energy-favorable regions for subsequent polycrystalline silicon thin film growth, i.e., nucleation sites (SS).

[0061] For example, in some embodiments of the present invention, the silicon substrate 100 can be a nitrogen (N) doped silicon substrate. Nitrogen atoms have a certain solid solubility and unique diffusion ability in silicon crystals. When the nitrogen-doped silicon substrate is heat-treated under precisely controlled temperature and atmosphere, the nitrogen atoms inside the silicon substrate are driven by thermal energy to diffuse and accumulate directionally towards the silicon surface. After diffusing to the surface, these nitrogen atoms combine with silicon atoms, forming discrete nucleation sites SS with well-defined size and distribution characteristics through interface energy minimization or chemical bonding. These nucleation sites SS are the preferred sites for the growth of polycrystalline silicon thin film grains, and their characteristics directly affect the grain structure of the final polycrystalline silicon thin film.

[0062] These nucleation sites (SS) do not form a continuous layer, but rather exist as preferential nucleation regions for the growth of polycrystalline silicon thin films. The inventors further discovered and utilized the principle that the average size and spatial distribution density of these nucleation sites (SS) can be effectively controlled by precisely controlling the nitrogen doping concentration, heat treatment temperature, duration, and furnace atmosphere. The principle is as follows: First, the inventors found that the nitrogen doping concentration directly determines the total amount of nitrogen atoms that can diffuse to the silicon substrate surface and participate in nucleation. Under otherwise constant conditions, a higher nitrogen concentration in the silicon substrate can provide more nucleation precursors, thereby facilitating the formation of a higher density of nucleation sites (SS). This provides more initial growth points for the subsequent grain refinement of the polycrystalline silicon thin film.

[0063] Furthermore, heat treatment temperature is a key factor affecting the diffusion rate of nitrogen atoms in silicon substrates. Through experimental and theoretical analysis, the inventors discovered that within a certain temperature range, higher temperatures result in faster nitrogen atom diffusion and a shorter time required to reach surface saturation and undergo nucleation. Simultaneously, temperature also affects the thermodynamic driving force of nucleation and the growth kinetics of nucleation sites (SS). Lower temperatures may lead to insufficient nitrogen atom diffusion and inadequate nucleation, resulting in smaller and less dense nucleation sites (SS). Higher temperatures, on the other hand, may promote rapid growth of nucleation sites (SS), even causing them to merge, leading to increased size and decreased density. By precisely controlling the temperature, it is possible to ensure that nitrogen atoms diffuse at an appropriate rate and form nucleation sites (SS) of ideal size and distribution on the surface.

[0064] Furthermore, the duration of heat treatment determines the cumulative amount and extent of nitrogen atoms diffusing to the surface and undergoing nucleation reactions. The inventors have discovered that, at a given temperature, a longer treatment time results in more nitrogen atoms diffusing to the surface, which is more conducive to the growth and maturation of nucleation sites (SS). Too short a duration may lead to insufficient nucleation or site inhomogeneity; while too long a duration may cause excessive growth and merging of nucleation sites (SS), resulting in decreased density and increased average size. Therefore, optimizing the duration is crucial for controlling the maturity and uniformity of nucleation sites (SS).

[0065] Furthermore, the furnace atmosphere significantly influences the surface state of the silicon substrate and the behavior of doped elements. For example, heat treatment can be performed in an inert atmosphere (such as high-purity argon or nitrogen) or a reducing atmosphere (such as hydrogen) to prevent oxidation of the silicon substrate surface at high temperatures and to ensure that nitrogen atoms can effectively combine with silicon to form nucleation sites (SS), avoiding interference from other impurities. The inventors have discovered that specific atmospheric conditions can alter the surface energy of the silicon substrate or the mobility of surface-adsorbed atoms, thereby affecting nucleation kinetics and indirectly controlling the size and density of nucleation sites (SS).

[0066] Taking a nitrogen-doped silicon substrate as an example, a high-resistivity silicon wafer undergoes rapid heat treatment at temperatures ranging from 600 to 1000°C. The duration of this heat treatment can be, for example, 10 to 60 minutes. By finely adjusting these parameters, the average size of the resulting nucleation sites (SS) can be controlled within the nanometer range, for example, from 20 to 40 nanometers. These controlled nucleation site characteristics are the key foundation for the precise control of the subsequent polycrystalline silicon thin film grain structure in this invention.

[0067] After the nucleation sites SS are formed, step S02 is performed, that is, a polycrystalline silicon thin film 10 is grown on the nucleation sites SS of the silicon substrate 100 to finally form the desired semiconductor substrate 1. The growth of this polycrystalline silicon thin film can be achieved using chemical vapor deposition (CVD) methods, such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). These methods can all achieve uniform deposition of the polycrystalline silicon thin film. For the growth of the polycrystalline silicon thin film, selecting a suitable CVD method is crucial to the characteristics of the final polycrystalline silicon thin film and the overall performance of the semiconductor substrate. Atmospheric pressure chemical vapor deposition (APCVD) has the advantages of high deposition rate, suitability for large-scale mass production, and relatively low cost. Low-pressure chemical vapor deposition (LPCVD) is renowned for its superior film uniformity and excellent step coverage. It is typically performed at lower pressures, which helps reduce gas phase reactions and improve film density and purity. Plasma-enhanced chemical vapor deposition (PECVD) is notable for its ability to deposit at relatively lower temperatures. It utilizes plasma to provide energy, promoting chemical reactions, and allows for flexible control over film stress, grain size, and defect density.

[0068] In some embodiments, regardless of the CVD method used, the growth temperature can be between 400°C and 1000°C, and the growth time can be between 10 minutes and 60 minutes to ensure that a polycrystalline silicon film with the desired thickness and grain structure is obtained. By precisely controlling these growth parameters and combining the characteristics of different CVD methods, this preparation method can obtain polycrystalline silicon films with ideal grain size, grain boundary density, and stress state.

[0069] By precisely controlling the heat treatment conditions to regulate the diffusion of dopants, nucleation sites SS with specific size and / or density are formed on the surface of a silicon substrate. The characteristics of these nucleation sites SS can directly and controllably affect the grain structure of the polycrystalline silicon thin film subsequently grown on them.

[0070] Specifically, there is a direct correspondence between the final grain size and / or grain density of the polycrystalline silicon thin film and the predetermined size and / or predetermined density of the nucleation sites (SS). The predetermined size and predetermined density of the nucleation sites (SS) can be understood as desired or set target values. These target values ​​can be set according to the final product requirements of the semiconductor substrate, such as the target electrical performance indicators of the semiconductor substrate. Furthermore, in order to achieve these predetermined size and density targets for the nucleation sites (SS), various process parameters (e.g., temperature, time, atmosphere, and doping concentration of heat treatment) and product indicators during the growth process (e.g., grain size and density of the seed layer) can be set accordingly. This correspondence enables the fabrication method to achieve precise control over the microstructure of the polycrystalline silicon thin film. For example, when the density of the nucleation sites (SS) is high, during subsequent growth, due to the simultaneous formation of more initial nuclei, the polycrystalline silicon thin film tends to form a finer, higher-density grain structure with more grain boundaries. When the nucleation sites SS are small in size and uniformly distributed, it may lead to the growth of more uniform and size-controlled grains in polycrystalline silicon films.

[0071] The semiconductor substrate fabrication method provided in this invention fundamentally solves the problem of maintaining stable grain size and grain boundary density in subsequent high-temperature processes during traditional polycrystalline silicon growth. By precisely designing and controlling the nucleation site SS precursor (e.g., by adjusting the doping concentration of the silicon substrate and the temperature and time of heat treatment), this fabrication method can purposefully construct polycrystalline silicon thin films with desired grain size and high grain boundary density, exhibiting excellent thermal stability. These high grain boundary density regions form a large number of carrier traps in the semiconductor material, effectively capturing and recombinating free carriers excited under the action of high-frequency electric fields, thereby suppressing their propagation and coupling in the substrate, significantly improving the equivalent resistivity and isolation performance of the substrate, and ultimately providing a good foundation for fabricating radio frequency integrated circuits that meet the requirements of high frequency, low loss, and high isolation.

[0072] To more intuitively demonstrate the technical effects of the present invention, Figures 5 to 9 together constitute a set of comparative experimental characterization results.

[0073] Specifically, Figures 6 and 8 show scanning electron microscope (SEM) images of the nitrogen-containing seed layer and nitrogen-containing polycrystalline silicon layer obtained by growing on a nitrogen-containing silicon substrate using the preparation method provided in this embodiment of the invention. Figure 6 clearly shows that the seed layer prepared by the method provided in this embodiment of the invention has very fine, dense, and uniformly distributed grains. Figure 8 shows that after subsequent growth, the grain size of the final polycrystalline silicon layer is still effectively suppressed, maintaining an overall small and uniform morphology.

[0074] In contrast, Figures 5 and 7 show nitrogen-free seed layers and nitrogen-free polycrystalline silicon layers fabricated on nitrogen-free silicon substrates using the same process, respectively. As shown in Figure 5, without nitrogen, the grain size of the seed layer is significantly larger than that in Figure 6. More importantly, as shown in Figure 7, during subsequent growth, the grains underwent uncontrolled growth, resulting in not only a significant increase in size but also significant variation and poor uniformity.

[0075] Figure 9 provides strong quantitative evidence for the aforementioned SEM images, clearly demonstrating the technical advantages of the embodiments of the present invention in the form of a box plot. This figure reveals two key messages:

[0076] First, precise control of grain size. Data series representing the preparation methods provided in the embodiments of the present invention ("with N-seed layer" and "with N-polycrystalline silicon layer") show that the average grain size is significantly smaller than that of the nitrogen-free comparative example and is precisely controlled within the target range (seed layer in the range of 20 nm to 40 nm, polycrystalline silicon layer in the range of 80 nm to 120 nm).

[0077] Second, it significantly improves grain uniformity. The two data series representing the preparation method provided in this embodiment of the invention have very narrow bins and short whiskers, which statistically indicates a highly concentrated grain size and excellent uniformity. This highly concentrated distribution results in the difference between the maximum and minimum grain size being significantly smaller than the average grain size (e.g., less than 50% of the average grain size). This contrasts sharply with the dispersed and highly varied grain size distribution in the comparative example (“w / o N” data series).

[0078] In summary, Figures 5 to 9 together demonstrate, both qualitatively and quantitatively, that by doping nitrogen into a silicon substrate, the embodiments of the present invention can effectively form fine initial grains and strongly suppress their growth during subsequent high-temperature processes, thereby obtaining a polycrystalline silicon microstructure with controllable size and high uniformity.

[0079] In some embodiments of the present invention, step S02 can be performed in two steps. Specifically, referring to FIG3, step S02 of growing a polycrystalline silicon thin film 10 on the nucleation site SS may include:

[0080] Step S021: Form a seed layer 11 on the nucleation site SS;

[0081] Step S022: A polycrystalline silicon layer 12 is grown on the seed layer 11. The resulting polycrystalline silicon thin film 10 includes the seed layer 11 and the polycrystalline silicon layer 12, with the seed layer 11 located between the silicon substrate 100 and the polycrystalline silicon layer 12. This stepwise growth strategy allows for more precise control over the overall microstructure of the polycrystalline silicon thin film, especially its grain size and grain boundary density.

[0082] The seed layer 11 refers to a thin layer of polycrystalline silicon formed directly on the nucleation sites of the silicon substrate 100, used to guide the growth of the subsequent polycrystalline silicon layer 12. Since the nucleation sites provide preferential nucleation regions of predetermined size and / or density, the initial grain structure of the seed layer 11 is directly affected by these nucleation sites.

[0083] Specifically, there is a direct correspondence between the grain size and / or grain density of the seed layer and the predetermined size and / or predetermined density of the nucleation sites.

[0084] The seed layer 11 is typically grown using chemical vapor deposition (CVD) methods, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The seed layer 11 can be grown within a specific temperature and time range, for example, at 900°C for 10 minutes. The grain size of the seed layer is in the range of 20 nanometers to 40 nanometers.

[0085] The polycrystalline silicon layer 12 is the main part that continues to be deposited and grown above the already formed seed layer 11, that is, the main part of the polycrystalline silicon thin film 10. The grain growth direction and size of this polycrystalline silicon layer 12 are directly guided and influenced by the grain structure of the seed layer 11 below. The seed layer 11 is equivalent to providing a template for the subsequent growth of the polycrystalline silicon layer 12, and its own grain characteristics, such as size, density, and orientation, determine the crystal continuity of the polycrystalline silicon layer 12 in the early stage of growth.

[0086] More importantly, during the later stages of polycrystalline silicon layer 12 growth or subsequent thermal processes, some nitrogen atoms diffuse further towards the grain boundaries and pin to them, effectively preventing further grain growth. By controlling the growth process parameters of polycrystalline silicon layer 12, such as growth temperature and growth time, the grain size, grain boundary density, and crystal orientation of polycrystalline silicon layer 12 can be further optimized.

[0087] For example, polycrystalline silicon layers can be grown using chemical vapor deposition (CVD) methods, including ambient pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The growth of polycrystalline silicon layer 12 can be carried out within a specific temperature and time range, such as growing polycrystalline silicon layer 12 at a temperature of 950°C for 30 minutes. The grain size of polycrystalline silicon layer 12 is in the range of 80 nanometers to 120 nanometers. Therefore, a hierarchically controlled, layer-by-layer microstructure regulation chain is formed between the nucleation sites, the seed layer 11, and the polycrystalline silicon layer 12.

[0088] Under suitable growth conditions, the average grain size of the polycrystalline silicon layer 12 is typically larger than that of the seed layer 11. More importantly, the pinning effect of nitrogen atoms at the grain boundaries effectively prevents the continuous growth of the polycrystalline silicon layer 12 grains during subsequent thermal processes, thereby ensuring the long-term stability of the grain structure and grain boundary density. This precise step-by-step control mechanism enables the present invention to optimize the overall grain size, grain boundary density, and thermal stability of the polycrystalline silicon thin film from the source, thereby obtaining a microstructure with more stable and efficient carrier trapping capabilities, effectively improving the performance of the semiconductor substrate in high-frequency applications.

[0089] Using the above-described preparation method, referring to Figure 4, the final semiconductor substrate 1 includes a nitrogen-doped silicon substrate 100 and a polycrystalline silicon thin film 10 formed thereon. As a composite layer with efficient carrier trapping capabilities, the overall characteristics of the polycrystalline silicon thin film 10 are crucial to the performance of radio frequency devices. The average grain size in the polycrystalline silicon thin film 10 is in the range of 80 nm to 120 nm. Furthermore, the grain size distribution of the polycrystalline silicon thin film is uniform; for example, the difference between the maximum and minimum grain size is less than 50% of its average grain size. These optimized overall microstructure features are key to achieving high resistivity and excellent isolation performance in this invention, ensuring the stability and reliability of the semiconductor substrate in high-frequency applications.

[0090] In some embodiments of the present invention, the nitrogen doping concentration of the silicon substrate 100 can be greater than 1E18 atom / cm³. This higher doping concentration, for example, for nitrogen in the silicon substrate, ensures that a sufficient number of dopant atoms can diffuse to the surface of the silicon substrate during subsequent heat treatment steps, thereby forming a sufficient number and density of nucleation sites. If the doping concentration is too low, the number of nucleation sites formed after heat treatment may be insufficient or unevenly distributed, failing to effectively guide the growth of polycrystalline silicon. Conversely, high doping concentration can provide a sufficient atomic source, ensuring the quality of nucleation site formation. At the same time, for nitrogen-doped silicon substrates, since nitrogen generally does not act as a major electrically active dopant in silicon to affect the conductivity pattern, even with high doping concentration, the high resistivity characteristics of the silicon substrate itself can be maintained.

[0091] In some examples, the resistivity of the semiconductor substrate 1 prepared by the preparation method provided in the embodiments of the present invention can be greater than 1000 ohm-cm.

[0092] As mentioned above, nitrogen atoms can be stably and uniformly introduced into silicon using mature processes such as the Czochralski (CZ) method. Specifically, in some embodiments of the present invention, the preparation method may include: pulling a nitrogen-doped single-crystal silicon rod; and cutting a silicon substrate 100 from the single-crystal silicon rod. This method specifically refers to directly introducing nitrogen during the silicon crystal growth process using single-crystal growth techniques such as the Czochralski method. This process ensures that nitrogen doping is highly uniform and controllable throughout the silicon rod, thereby guaranteeing that each silicon substrate obtained after subsequent cutting has a uniform nitrogen content, laying the foundation for the formation of high-quality, uniform nucleation sites. Silicon single-crystal rods produced by the Czochralski method have advantages such as high purity, large size, and low defect density, which are highly compatible with the requirements of the embodiments of the present invention for high-performance radio frequency substrates, and also fully utilize the industrial foundation and cost advantages of semiconductor manufacturing in related technologies.

[0093] In some embodiments of the present invention, the resistivity of the nitrogen-doped silicon substrate 100 of the semiconductor substrate 1 can be greater than 1000 ohm-cm, and the resistivity of the polycrystalline silicon thin film 10 of the semiconductor substrate 1 can also be greater than 1000 ohm-cm.

[0094] High-resistivity silicon substrates and polycrystalline silicon thin films are crucial for realizing high-performance radio frequency (RF) components. By ensuring that both materials maintain high resistivity, substrate dielectric loss, eddy current loss, and parasitic coupling effects can be effectively reduced, thereby ensuring the integrity and high isolation of RF signals. According to embodiments of the present invention, by controlling the formation of nucleation sites and the pinning of grain boundaries by nitrogen atoms, the polycrystalline silicon thin film forms a small and dense grain structure, effectively capturing free carriers and maintaining its inherent high resistivity characteristics. This allows both materials to maintain their inherent low carrier concentration and jointly contribute to the overall high resistivity of the substrate. Ultimately, this will significantly improve the power efficiency, sensitivity, and bandwidth performance of RF components.

[0095] Example

[0096] The following examples and comparative examples are intended to illustrate in detail the specific implementation of the present invention and to verify the significant technical effect of the present invention in precisely controlling the microstructure of polycrystalline silicon thin films (especially grain size and uniformity).

[0097] Example 1

[0098] This embodiment aims to prepare a semiconductor substrate with a small-sized, highly uniform grain structure of polycrystalline silicon thin film, which includes the following steps:

[0099] Step 1: Silicon substrate preparation: A high concentration of nitrogen (>1E18 atom / cm³) is doped during the pulling of a high-resistivity crystal ingot using the Czochralski method. The nitrogen-doped silicon substrate 100 is then cut from this ingot. The resistivity of this silicon substrate is measured to be greater than 1000 ohm-cm.

[0100] Step 2, Nucleation Site Formation: The silicon substrate 100 obtained in Step 1 is subjected to rapid thermal processing (RTP). The heat treatment temperature is set to 900°C and the duration is 10 minutes. This step aims to allow nitrogen atoms inside the silicon substrate to diffuse to the surface, forming uniformly sized nucleation sites SS.

[0101] Two-step growth of polycrystalline silicon thin films:

[0102] Step 3a (seed layer growth): The silicon substrate treated in step 2 is placed in an LPCVD device and deposited at 900°C for 10 minutes to form a seed layer 11.

[0103] Step 3b (Polycrystalline silicon layer growth): Continue deposition in the LPCVD equipment at a temperature of 950°C for 30 minutes to grow a polycrystalline silicon layer 12 on the seed layer 11.

[0104] Performance Results and Characterization:

[0105] The final semiconductor substrate was subjected to SEM and image analysis, and the results are shown in Figures 6, 8, and 9:

[0106] Seed layer: The formed seed layer 11 has an average grain size in the range of 20 nm to 40 nm (see Figure 9, “with N-seed layer” data).

[0107] Final polycrystalline silicon film: The final polycrystalline silicon film 10 has an average grain size in the range of 80 nm to 120 nm (see Figure 9, “with N-polycrystalline silicon layer” data).

[0108] Grain uniformity: The grain size distribution of the polycrystalline silicon thin film 10 is highly uniform. The difference between its maximum grain size (approximately 120 nm) and minimum grain size (approximately 80 nm) (40 nm) is less than 50% of its average grain size (approximately 100 nm) (calculated value is 40%).

[0109] Resistivity: The resistivity of the polycrystalline silicon thin film 10 was finally measured to be greater than 1000 ohm-cm.

[0110] Comparative Example 1

[0111] This comparative example aims to illustrate the decisive role of nitrogen doping in controlling the grain size and uniformity of polycrystalline silicon thin films.

[0112] Silicon substrate preparation: The same Czochralski process is used, but without nitrogen doping, to obtain a common silicon substrate with high resistivity (>1000 ohm-cm).

[0113] Process steps: The process used is exactly the same as that in Example 1, which involves heat treatment (900°C, 10 minutes) and a two-step growth of polycrystalline silicon thin films (seed layer 900°C / 10 min, polycrystalline silicon layer 950°C / 30 min).

[0114] Performance Results and Characterization:

[0115] The final semiconductor substrate was subjected to SEM and image analysis, and the results are shown in Figures 5, 7, and 9:

[0116] Seed layer: The average grain size of the formed seed layer has increased to the range of 60 nm to 100 nm (see Figure 9, “w / o N-seed layer” data).

[0117] Final polycrystalline silicon film: The final polycrystalline silicon film has significantly coarsened grains, with an average grain size in the range of 100 nm to 200 nm, far exceeding the target range of the embodiments of the present invention (see Figure 9, "w / o N-polycrystalline silicon layer" data).

[0118] Grain uniformity: The grain size distribution of polycrystalline silicon films is extremely non-uniform. The difference between the largest grain size (about 200 nm) and the smallest grain size (about 100 nm) is much greater than 50% of the average grain size (about 160 nm) (calculated value is about 62.5%).

[0119] Summary of Examples and Comparative Examples

[0120] The results of comparing Example 1 and Comparative Example 1 clearly show that:

[0121] Size control: Under the same heat treatment and growth process, the nitrogen-doped silicon substrate of the present invention (Example 1) can precisely control the final polycrystalline silicon grain size within the target range of 80~120 nm. In contrast, the undoped silicon substrate (Comparative Example 1) exhibits uncontrolled grain coarsening, with the size far exceeding the target range.

[0122] Uniformity control: The polycrystalline silicon thin film prepared by the present invention (Example 1) exhibits excellent grain size uniformity (size difference / average size <50%), as shown in Figures 8 and 9. In contrast, the grain size of Comparative Example 1 is very discrete and has poor uniformity, as shown in Figures 7 and 9.

[0123] The conclusion shows that nitrogen doping in silicon substrates is a key element for achieving precise control over the grain size and uniformity of polycrystalline silicon thin films. By providing a high density of nucleation sites in the early stages of growth and pinning grain boundaries in the later stages, it effectively suppresses abnormal grain growth during high-temperature processes, thereby obtaining a microstructure with small size, high uniformity, and high stability, laying a solid foundation for improving the performance of radio frequency devices.

[0124] It should be noted that the technical solutions described in this invention can be combined arbitrarily without conflict.

[0125] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of protection of the aforementioned patent claims.

[0126] 1: Semiconductor substrate 10: Polycrystalline silicon thin films 11: Seed layer 12: Polycrystalline silicon layer 100: Silicon substrate SS: nucleation site S01, S02, S021, S022: Steps

Claims

1. A method for preparing a semiconductor substrate, the method comprising: A nitrogen-doped silicon substrate is heat-treated to diffuse nitrogen from the substrate to the surface of the substrate, thereby forming nucleation sites of a predetermined size on the surface of the substrate. A polycrystalline silicon thin film is then grown on the nucleation sites to form a semiconductor substrate.

2. The method for preparing a semiconductor substrate as described in claim 1, wherein, The growth of a polycrystalline silicon thin film at the nucleation site includes: forming a seed layer at the nucleation site; and growing a polycrystalline silicon layer on the seed layer.

3. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The nitrogen doping concentration in the silicon substrate is greater than 1E18atom / cm3.

4. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The heat treatment is a rapid heat treatment at 600°C to 1000°C.

5. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The size of the nucleation sites is in the range of 20 to 40 nm, and the grain size of the polycrystalline silicon film is in the range of 80 to 120 nm.

6. A method for preparing a semiconductor substrate as described in claim 5, wherein, In the polycrystalline silicon thin film, the difference between the maximum and minimum grain size is less than 50% of its average grain size.

7. A method for preparing a semiconductor substrate as described in claim 2, wherein, The step of forming the seed layer includes: performing a heat treatment at a temperature of 900°C for 10 minutes to form the seed layer with a grain size in the range of 20~40 nm.

8. A method for preparing a semiconductor substrate as described in claim 7, wherein, The step of growing a polycrystalline silicon layer on the seed layer includes: performing a heat treatment at a temperature of 950°C for 30 minutes to form the polycrystalline silicon layer with a grain size in the range of 80~120 nm.

9. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The steps for growing polycrystalline silicon thin films include: growing polycrystalline silicon thin films using atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

10. A method for preparing a semiconductor substrate as described in claim 9, wherein, The step of growing the polycrystalline silicon thin film is carried out at a temperature of 400~1000℃ for a duration of 10~60 minutes.

11. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The semiconductor substrate has a resistance greater than 1000 ohm-cm, and the polycrystalline silicon thin film has a resistivity greater than 1000 ohm-cm.

12. A method for preparing a semiconductor substrate as described in claim 1 or 2, wherein, The preparation method further includes: pulling a nitrogen-doped single-crystal silicon rod; and cutting a nitrogen-doped silicon substrate from the single-crystal silicon rod.

13. A semiconductor substrate, said semiconductor substrate comprising: Nitrogen-doped silicon substrate; And a polycrystalline silicon thin film disposed on the silicon substrate; wherein the average grain size of the polycrystalline silicon thin film is in the range of 80~120 nm, and the difference between the maximum grain size and the minimum grain size in the polycrystalline silicon thin film is less than 50% of its average grain size.

14. The semiconductor substrate as described in claim 13, wherein, The polycrystalline silicon thin film includes: a seed layer formed on the silicon substrate; and a polycrystalline silicon layer formed on the seed layer.

15. The semiconductor substrate as described in claim 13 or 14, wherein, The nitrogen doping concentration in the silicon substrate is greater than 1E18atom / cm3.

16. The semiconductor substrate as described in claim 14, wherein, The average grain size of the seed layer is in the range of 20~40 nm.

17. The semiconductor substrate as described in claim 13 or 14, wherein, The resistivity of the silicon substrate is greater than 1000 ohm-cm, and the resistivity of the polycrystalline silicon thin film is greater than 1000 ohm-cm.

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